My attempts at a design of a 3 stage amplifier

Simulations with the servo posted by Mooly worked. Again, the very good distortion figures did not suffer as a result of this addition. The short circuit current is composed of triangular pulses with a base of 23uS and peak of 33A. The frequency of these pulses is 1000Hz. With higher frequencies the triangular base is shorter but the frequency is higher. It is indicative at high frequencies short circuiting the output has a higher probability of causing damage. For this reason, caution can never be ignored.

I am attaching the latest version of the schematic. The good news about this is the actual physical circuit only needs additions with no deletions. I made a big effort to achieve that goal. The actual physical circuit works and it would be a real pity to dismantle it.
 

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If a Thiele stability network is a must have then C10 at 1uF is ten times what it ought to be. 1kHz is a much easier test frequency for THD than 20kHz the loading on your amplifier will be increased by 20 times due to the reduced impedance of C10 at 1uF.

I have suggested getting rid of the 1uF for that reason on more than one occasion. You should test for THD at 20kHz and run a 10kHz square wave test as well before going ahead with your build.
 
The 1uF accounts for the worst case scenario of powering a speaker with very long speaker cables. In my very first posts of this thread, I was warned that with the kind of voltages used in this amplifier, when using very long speaker cables, amplifier can self oscillate. So, the 1uF is not part of the circuit, but it represents the speaker cable's parasitic capacitance.

The THD is often quoted for 1kHz but I am also simulating for 16kHz to calculate the THD at the topmost end of the human acoustic spectrum. These figures are higher than what is obtained at 1kHz but they are still below 0.2%.

The square wave test was also conducted. Since there is a parallel inductor resistor network in series with the load, there is some ringing but not at RF frequencies. I remember, earlier in this long thread, similar charts have been judged as good results.

I would like to ask some electronics guru who deeply understands the behaviour of real life components, whether using an opamp to correct the DC offset voltage, would also correct the stray voltages that caused the crackling and the mains hum/buzz? I remind any readers that the latter imperfections were quite weak.

My reasoning goes something like this. The hum, buzz and crackling are not part of the signal. So, they are not accounted for in the input stage and should be seen as extraneous voltages without an input drive. Because of this, they should also be cancelled by the opamp.

I remind readers I am fallible, and my insight might not be as deep and refined as reality.
 
A DC servo does not correct output deviations from the input signal, but from Zero Volts. Its reaction time it slowed down to seconds on purpose, or it would ‘correct’ the music as well, leaving nothing.

So no, it cannot reduce crackling and buzzing, it cannot distinguish them from (wanted) music. It just keeps the _average_ output voltage at zero.

What you mean is error correction, or just negative feedback.
 
The 1uF accounts for the worst case scenario of powering a speaker with very long speaker cables. <snip>

The servo will not resolve the issues you have raised already pointed out. It is good to see you have abolished the zener diode reference for the cascode in the LTP in the simulation and replaced that with a resistor with a parallel capacitor. If you have not implemented that in the actual hardware you should test to see what difference that makes. The way you drew up the circuit suggested the zener current flowed through the earth reference point for the nfb decoupling arm to earth which is not in keeping with best practice.

The worst imaginable scenario is that of having the transformer centre tap to earth or the supply current to earth currents flowing through the input earths for noninverting and inverting LTP as these will result in the sorts of results you describe.

The correct way to wire up an amplifier has been the subject of recent discussion here -How to wire up an Amplifier
 
It is good to see you have abolished the zener diode reference for the cascode in the LTP in the simulation and replaced that with a resistor with a parallel capacitor. If you have not implemented that in the actual hardware you should test to see what difference that makes. The way you drew up the circuit suggested the zener current flowed through the earth reference point for the nfb decoupling arm to earth which is not in keeping with best practice.
The mentioned changes has been implemented in the hardware. According to my hearing, it seems, the issues have been attentuated, but I am cautious to be objective. Confirmation bias is something I want to guard against.

The worst imaginable scenario is that of having the transformer centre tap to earth or the supply current to earth currents flowing through the input earths for noninverting and inverting LTP as these will result in the sorts of results you describe.
The zero volt terminal from the power supply is the terminal that conducts most current. This means, hum and buzzes are superposed on the theoretical 0V. For this reason, all decent electronic textbooks introduce novice learners to the practice of using a star ground with no loops. The 'centre' of the star is the point where a power supply feeds its current; the many star arms are used for the various subcircuits including signal subcircuits. To avoid coupling of hum and buzzes, the centre point is also where an electrolytic capacitor is connected. The same technique is used for the supply rails. Relatively long tracks are further supply decoupled using small electrolytic capacitors, which may also have pF ceramic capacitors in parallel.

Added Later; an anecdote:
Throughout this journey, I was always curious to understand, why the input stage's current source experiences modulation of its output current. Yesterday, a bell rang in my not so alert mind, that the differential pair's emitters follow the input signal voltage. This means, if a signal is 2V peak to peak, the differential pair's emitters also experience a 2V peak to peak voltage swing. This swing effectively changes the voltage seen by the current source's collector resulting in a collector current modulated by emitters_voltage_swing/Ro, where Ro is the current source's output impedance.

The most vexing analytical complexity of transistors, is the fact, most parameters are non-linear, and our human brain, is not very well equipped to predict the value of non-linear relationships. The transistor itself is an exponential device with currents starting to flow from well below the greatly simplified 0.7V of Vbe.

Something I would like to ask is whether bipolar transistors operate using the curious Quantum Mechanical effect of tunnelling. A bipolar transistor is a silicon die with three distinct 'impurity' diffusions with the base region having the least of diffusions. The signs of diffusions are such that two depletion layers are formed, one at the boundary of the emitter and base, and the other at the boundary between base and collector. The polarities are such that the equivalent of two diodes back to back are formed. So, under normal conditions, no current should reach the third layer from the first. However, and this however is very curious and interesting, when a small forward voltage is applied to the emitter base region, electrons will be accelerated into the base gaining kinetic energy, that is enough for them, to shoot straight into the collector region, notwithstanding the presence of an inhibiting electric field. According to what I can recall from Physics, this is Quantum Tunnelling. Am I correct?
 
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I resolved all the earthing issues I had with the methods described in the link provided. With a magnetic cartridge and full volume there is no audible hum at all.

Modern transistors are planar. As I understand it a PN junction would be made by diffusing a P impurity material into a wafer of N type material so where these doped areas of material come into contact you will have a greater amount of P type silicon on one side of a boundary and a greater amount of N type silicon on the other.

Thus being in intimate contact electrons will diffuse across the boundary so the Fermi levels on both sides are equal causing a relative shift in electrical potential between the two sides.

For the rest on what happens as a consequence of this there are plenty of resources you can study on the web that you can access for further information.
 
Sadly, the web has become an unreliable resource for objective scientific research and learning. Filtering search results, where permitted, can help, but if a learner needs advanced texts, one is faced with getting only opinions, and very basic material. Please, do not suggest wikipedia, or similar open resources that can be edited by anyone. These are very very unreliable. It seems to me, notwithstanding of the advent of the internet, one is back to square one, when the internet did not exist: only good quality books from reputable publishing houses can guarantee high quality scientific and technical texts.
 
Self Oscillations Demystified:

The nasty phenomenon of negative feedback disguising itself into positive, and causing self sustained oscillations in a differential amplifier, has been a temptation to study in more detail since I started this project. Not only does this phenomenon, makes the design of an amplifier, excruciatingly difficult to stabilize, but it also requires, the use of signal processing transistors with matched collector current handling.

So far, I learnt a bipolar transistor always present an emitter-base capacitance albeit extremely small. This small capacitance is effectively in series with the input resistance and forms a low pass RC filter. The useful signal is across the capacitor, which means, as the input frequency is increased, the voltage across the capacitor will eventually cease to cause any current to flow through the base-emitter region. As if this is not enough, the collector-base region also has another capacitance which manifests itself across the load stealing useful power if the frequency is high enough.

A third unwanted phenomenon is the consequence of having parasitic low pass filters. RC filters cause signal phase change, and with an amplifier built of several stages, this phase change is cumulative. When the total phase change reaches 180 degrees, negative feedback changes its status into positive feedback, with the consequence, any frequency causing a phase change of pi + 2*pi*n = pi(1 + 2n), n is an integer, will setup a self sustained oscillator (expression is in radians).

To add insult to injury, the output capacitance of bipolar transistors is voltage dependent. This capacitance drops with increasing collector-base voltage. This property, explains why high power amplifiers, have the habit of oscillating at high outputs, and mysteriously staying quiet at lower outputs. The explanation for this behaviour is something like this: during a wide output voltage swing, the output capacitance of transistors goes from high to low, consequently, the phase change also changes. However, at particular voltages, the phase change, might be an odd multiple of pi radians, and hence, one gets ghostly sparodic oscillations superposed on the output.

The solution to all these unwanted oscillations, is to limit the high frequency bandwidth, and the number of amplifier stages, as having more stages, is having more phase changes which can easily add up to odd multiples of pi radians for a particular frequency.

Readers should understand, there is nothing religious or dogmatic about Miller Capacitances as normally used in amplifiers. Any low pass filter that does not affect the amplifier's linearity and that limits the high frequency bandwidth, can be used. However, Miller's solution is one of the simplest to use.
 
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This is an attempt to explain the cause of the 'ghostly' superposed oscillations at high voltage output.

Since the load is in series with the output transistors, the active transistors at high voltage output, have low Vbc. This means, the base-collector capacitance is higher compared to when the output is low. So, there is an increased probability a resonant frequency falls in the amplifier's frequency response, as such a resonant frequency, drops with increasing capacitance.
 
Common Mode Rejection Ratio:
The issue of crackling, noise and distorted hum, although very slight, may be an indication of insufficient common mode rejection. Since here it is Summer, and the temperatures are too hot to even tolerate the presence of an unplugged soldering iron, I am focusing my efforts on investigative theory. Crackling, white/brown noise and hum are not sourced from the input, but should be sourced by external sources. If this is true, then, insufficient common mode rejection may be the real cause.

I am again attaching the final circuit schematic, for which I would like to find a formula to calculate the common mode rejection ratio, and if it makes sense, the common mode gain. The common mode gain should tell us, the effect of V1 + V2, instead of V1 - V2, (V1 and V2 are the input signals).
 

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I beg pardon for posting again, but, the hum and crackles issues will not solve themselves unless I find and understand their real cause. My studying of opamps attributes hum at the output of opamps to insufficient common mode rejection and crude power supplies. The latter, is impossible, but the former is a possibility.

Common mode amplification is the 'other' unwanted amplification process besides differential amplification, which is often accounted for and wanted.

To investigate common mode amplication, I made sure the input difference at the inputs is zero. I achieved this by shorting the inputs together in LTSpice. In agreement with my expectations, the output is not zero, but a replica of the power supply ripple but with a much attenuated amplitude. This means, the differential input is not rejecting common mode signals sufficiently.

I am attaching a screenshot of the output and positive rail voltage.
 

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The cascode at the input stage is subjected to power supply ripple and mains impurities. The cascode's changing Vbc causes its output currents to be modulated in accordance with the cascode's transistors output characteristic. So, the current mirror is receiving all these blemishes, and due to itself not being a totally balanced mirror, some of these blemishes are passed on to the VAS.

The sources of this problem are the transistors' finite output impedance/resistance and not-perfectly matched current mirror transistors.
 
Further explanation:
Since the bases of the differential pair are shorted together, the output is generated as a result of the finite BJT output impedance. The cascode's collectors are effectively under the influence of the positive rail voltage which, like all power supplies, has a ripple and voltage artifacts arising from the mains. The current mirror is seeing current artifacts on both sides. Consequently, the output voltage of the current mirror is oscillating in synchrony with these artifacts, and a portion of current is fed to the VAS.

The solution is to increase the cascode's output impedance by a factor of several times that is sufficient to get a zero signal output. In theory, this is a flat output response that is not obtainable while keeping the circuit simple.

Online I found several ways of improving the input stage's current mirror and cascode, but all of them, involve the use of MOSFETs, and are targeted to be used in integrated circuits, where the number of components is not a limitation.

At this point, I am alone in this quest of perfectioning my already good amplifier. As I wrote earlier, I stopped making hardware changes due to the Summer heat. I am using my free time to delve deeper and deeper into what is causing these issues, albeit being minor for the power handled.

I will simulate the effect of linearising transistors on the transistor's output impedance. In such an arrangement, when Ic increases, a corresponding increase is set up across Re, a linearising transistor feels this increase, and correspondingly steals some base drive from the linearised transistor. This causes the output current to be less dependent of Vcb, which is an increase of the transistor's output impedance.
 
You appear to plot V(out) rather than the drive to the VAS. The supply ripple may be coming from the VAS rather than input stage - unless you've ruled that out somehow?
Plotting Ic for both cascode transistors, it was very evident the ripple and power supply artifacts, are influencing the input stage's output. The telltale undulations can be clearly distinguished.

Have you plotted the common mode current output of the cascode on the input stage directly?
Yes, I started my investigation by looking at what is happening in the cascode, and immediately confirmed the telltale signs are present.

Increasing a BJT's output impedance using simple circuit alterations seems quite difficult to achieve. Trying the same trick used in linearising BJT's emitter-base junctions did help to some extent, but it is clearly, this is not an optimal way of going about to solve the issue.

If my wetware (brain) serves me right, I recall reading that an input stage's current source, is a strong determinant of common mode rejection.

I will investigate the value of the cascode's Ic1 + Ic2 and compare it with the current source's output current. The reason for this is to get more insight into what is actually happening.

There is a current difference of 12uA which is reasonable for the differential's base currents. The waveforms match.
 
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I beg pardon for posting again, but, the hum and crackles issues will not solve themselves unless I find and understand their real cause. My studying of opamps attributes hum at the output of opamps to insufficient common mode rejection and crude power supplies. The latter, is impossible, but the former is a possibility.

Common mode amplification is the 'other' unwanted amplification process besides differential amplification, which is often accounted for and wanted.

To investigate common mode amplication, I made sure the input difference at the inputs is zero. I achieved this by shorting the inputs together in LTSpice. In agreement with my expectations, the output is not zero, but a replica of the power supply ripple but with a much attenuated amplitude. This means, the differential input is not rejecting common mode signals sufficiently.

I am attaching a screenshot of the output and positive rail voltage.

I believe what you are seeing here is the headaches one can have with star ground and output load line limiters.

The last simulation I copied starts to clip if the input voltage is raised too much above 0.9V at which point the peak voltage on sine at 1kHz is 45V - which is less than 150W rms into 8R.

With 72 volt rails this is coming up short.

The plot at 45V peak out for the positive rail is a straight line at 72V whether or not the output stage has reverse bias protection diodes in parallel.