My attempts at a design of a 3 stage amplifier

First, I will admit to myself that these attempts may prove useless.

After so much head scratching, I inputted the input stage of what I think the input stage should look like. I am using the CAD hog named KiCad. It is a huge piece of software that probably requires one to buy a book to even start using it. As you can see, I haven't figured out how I can neatly display the various texual descriptions displayed next to components.

The attachment is the first stage as I am imagining it. I will use a cascode to isolate the input from the high voltage of the power supply. I am aiming to first make the input stage, test it to make sure it meets its required standard and then proceed to the VAS. The power stage is already built as it was part of a large public address amplifier that failed. I will usethe PA amplifier's chassis, power supply and power stage and redesign the pre-driver stages.

You may deem me mad, but sometimes being mad may be the only adventurous and successful route.

I am posting both for your comments (criticism) and hints about how I can use KiCad to get a better looking schematic and for improvements that I can make to the input stage.

Thanks to all those who made this website a reality and to those who will contritbute to this thread.
 

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I can't answer your KiCad question, but would say that if your are interested in both drawing circuits on screen (and if you wish simulating them as well) then LTspice might be worth looking at.

As to your circuit, well the most obvious problem at the moment is you have all NPN transistors as drawn whereas the upper two should be PNP's while the lower NPN appears to be the wrong way around. Not quite sure what you are intending the lower one to do actually :)
 
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I am seconding Mooly's reply with a stronger recommendation that you use LTspice simulator. The circuit as drawn cannot work so there is no point in a prototype.

LTspice will prove the concept functionally. Although simulation cannot emulate with 100% accuracy, it will save you a heck of a lot of time. It is also standard procedure for this site, as it makes collaboration with others more productive.

LTspice is also free. Your bank/mattress account is safe.
 
I am on Linux, Devuan ASCII. Installing more software means more time dedicated to setup software that I have never used in my life. Using KiCad my concentration is more focused on the new commands that I am learning to use rather than the components. Yes, as mentioned to me, there were 3 transistors that should be PNP: the two comprising the current mirror and the transistor at the bottom negative power rail. Software teething problems are distracting me from focusing on circuit design and on doing circuit calculations to make sure everything works within planned currents and voltages.

The lower part of the circuit consists of a series pass voltage regulator which powers a current source that is used to supply a constant current to the differential pair. The voltage of the differential pair is truncated using a cascode so that they work with a voltage of around 6.8V - 0.7V = 5.9V. According to Douglas Self, I should try to use a constant current of 6mA but I find this a little too high. I know there are amplifiers that use less about 2.5mA. I am still hesitant about using a current mirror as the interface for the differential pair. I think, using a complementary pair of small signal transistors with their bases connected to both heads of the differential pair, can also work and ensure the differential pair always conduct nearly equal currents.
 

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I disagree. The most obnoxious CAD tools I’ve used have all been closed source (Cadence comes to mind as being particularly awful to use). I took a couple of days to bring myself up to speed on KiCAD from a background in Altium/Protel and Cadence, and now prefer KiCAD strongly from an ease of use perspective.

KiCAD is reasonably straightforward, plus very powerful. And being open is huge. I am so over the bloated crap and enforced updates from, for example, Altium.
 
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I'm with suzyj.

Altium is more powerful than KiCAD, but I like using KiCAD better. EAGLE is a distant third behind both, and DxDesigner/PADS has similar or more capability than Altium but a far more frustrating UI.

Unless I'm routing something like a 64-bit 800MHz DDR3 data bus, KiCAD is my favorite. Altium irritates me multiple times a day.
 
I am on Linux, Devuan ASCII. Installing more software means more time dedicated to setup software that I have never used in my life. Using KiCad my concentration is more focused on the new commands that I am learning to use rather than the components.
No, man, you’re too fast and early with KiCAD.

As far as i see you’re trying to design relatively deep-feedback amplifier. Putting current mirrors in a load of differential stage will give you at least ~50 dB gain, next stage (obviously known as VAS) will provide you with additional ~50-60 dB.

This is really a Niagara-waterfall of gain and you must gently curb it or it will destroy your amplifier while you build and powerup your amp.

First read this:
http://www.ti.com/lit/an/sboa015/sboa015.pdf
Next go here:
http://u.dianyuan.com/upload/space/2010/12/30/1293704376-389780.pdf
And there:
https://kenkundert.com/docs/cd2001-01.pdf

Not matter how your feedbacked amp designed in its core (we could discuss this also) it must meet stability requirements.
 
I understand that using a current mirror as load in the differential input stage increases gain, but do not understand how a non-linear bias, that is, the diode connected transistor, which drives the other transistor, results in a linear configuration. I may understand that since we are talking about a current mirror, the currents in both transistors are restricted to remain EQUAL. So, this should mean, that the drop in current in one arm, say dIa, must be accompanied by a similar drop in the other arm. This means the overall current drop that must be diverted away from the current mirror is 2*dIa. This diverted current, I presume must flow into the VAS.

I think, I understood it. Since, the differential pair is made to operate with balanced arm currents, it is extremely linear, and since the current mirror's action is to divert current changes into the VAS, the arrangement must be a very linear transconductance stage.

Thanks to all who took some of the their time to answer this thread and also for the reading resources.

P.S.
I will draw the entire circuit as it is bubbling in my mind so that users would know what I am after. I know, I must study the circuit's stability scrupolously before attempting to power it up although testing on the input stage alone should not result in damaged components.
 
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I understand that using a current mirror as load in the differential input stage increases gain, but do not understand how a non-linear bias, that is, the diode connected transistor, which drives the other transistor, results in a linear configuration. I may understand that since we are talking about a current mirror, the currents in both transistors are restricted to remain EQUAL.
Yes. It remain equal until overload/clipping circumstances. There are no nonlinear bias, there are just loading first shoulder by the equal current to the second shoulder. This is mostly like to very high resistance load which greatly increases gain of the common-emitter stage.

Thanks to all who took some of the their time to answer this thread and also for the reading resources.
Also proceed with this: https://www.diyclassd.com/img/upload/doc/an_wp/WP_AES123BP_the_engineers_survival_guide.pdf

I will draw the entire circuit as it is bubbling in my mind so that users would know what I am after. I know, I must study the circuit's stability scrupolously before attempting to power it up although testing on the input stage alone should not result in damaged components.
Now basic rule is to pick as much gain as possible and to create as wide as possible output stage. Drawing or simulating stages as is not a good idea since they will operate at a totally different conditions while feedback loop will be closed.
 
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I am posting a jpg of the circuit so that users will know what I am after. The circuit is by no means a finalised version as it is practically my first attempt and I am not an electronics engineer. The circuit still has no output current overload protection and no clipping detection which is a must for high power amplifiers.
 

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1k4 for the lower current sink only gives around 0.9 ma VAS current which would normally be considered to low. Typically would be in the range of 5 to 9ma depending on the overall design.

120k input bias resistor should ideally match the feedback resistor for best DC balance.

Using a PNP device for the VAS is fine although perhaps a little more limiting in choice of devices available. A single lowish gain device like the MJE350 will also tend to load the front end.

The bias setting resistor network and preset seem very arbitrary and somewhat high in value.

The driver stage may struggle to supply four output pairs under full drive. The driver arrangement with 68 ohms are the limiting factor.
 
1k4 for the lower current sink only gives around 0.9 ma VAS current which would normally be considered to low. Typically would be in the range of 5 to 9ma depending on the overall design.
The next stage is a buffer so that the current drawn from the 1st stage of the VAS is negligible. This is why I chose to use a low current, 1mA.

120k input bias resistor should ideally match the feedback resistor for best DC balance.
This means, I will need to recalculate the values for the input filters.

Using a PNP device for the VAS is fine although perhaps a little more limiting in choice of devices available. A single lowish gain device like the MJE350 will also tend to load the front end.
The first stage of the VAS is buffered. If I am mistaken please enlighten me. I do not want to appear rude.

The bias setting resistor network and preset seem very arbitrary and somewhat high in value.
The amplified diode must provide a constant voltage of around 0.7*2 + 1.2V = 2.6V. The 1.2V was determined using another circuit driving the output stage. In the circuit there are four bases in 'series', which means a bias voltage of around 0.7V*4 is to be expected.

The resistor values of the amplified diode were calculated as follows.

The Emitter-Base junction voltage drop was assumed to be 0.7V with a parallel resistance of 7000 Ohms. This means, 100 micro amps flow in the preset and 6k resistor. 100E-6*19000 = 1.9V. So, that the total amplified diode voltage is 1.9V + 0.7V = 2.6V. Assuming beta to be around 50, for 1mA collector current, the base current would be 20 micro-amps.

The driver stage may struggle to supply four output pairs under full drive. The driver arrangement with 68 ohms are the limiting factor.
The resistance value is 6.8 Ohms. The output stage is known to work as it was part of a public address amplifier that failed.
 
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Your story so far :)

The bias setting voltage in practice is quite critical and a change of just a few millivolts will alter the bias current significantly. You can never calculate the value of the resistors needed, all you can do is ensure there is sufficient range on the bias trimmer.

I would have made the values lower which would totally swamp any changes in transistor parameters vs temperature.

The VAS is Q9 in my diagram and that really needs to be something 'better' than a lowish gain MJE350.

A few of your resistor values are hard to read on the diagram and so I had to guess at what you wrote. Although I've quickly looked it over there could be some odd errors in copying your circuit although nothing jumped out.

The DC conditions look basically OK. I've set the bias to around 35ma per pair. I also added a Zobel network but there was no real change to the stability as yet... so more work needed ;) As you can see, its oscillating like crazy at the moment.
 

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Your story so far :)

The bias setting voltage in practice is quite critical and a change of just a few millivolts will alter the bias current significantly. You can never calculate the value of the resistors needed, all you can do is ensure there is sufficient range on the bias trimmer.

I would have made the values lower which would totally swamp any changes in transistor parameters vs temperature.
That requires the use of a higher VAS current. I will recalculate the component values for a current of 7mA. This should reduce the resistor value by 7 times.

The VAS is Q9 in my diagram and that really needs to be something 'better' than a lowish gain MJE350.
I will try to replace it with a transistor of higher gain.

A few of your resistor values are hard to read on the diagram and so I had to guess at what you wrote. Although I've quickly looked it over there could be some odd errors in copying your circuit although nothing jumped out.
The capacitor in the negative feedback track is 2200 micro Farads.

The DC conditions look basically OK. I've set the bias to around 35ma per pair. I also added a Zobel network but there was no real change to the stability as yet... so more work needed ;) As you can see, its oscillating like crazy at the moment.
Getting an oscillator instead of an amplifier how embryonic amplifiers welcome their designers. My first amplifier first oscillated at 660kHz with the output stage getting hot. I readjusted the bias and added a Miller capacitor and the problem was solved but this circuit is more complicated and more challenging.
 
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An old saying, amplifiers always oscillate and oscillators often fail to do so.

I had missed a ground off the 2200uF cap. It all basically works once that was corrected. Changing the input components has brought the offset down to around 5mv. The AC response looks a little peaky though.
 

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