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My attempts at a design of a 3 stage amplifier
My attempts at a design of a 3 stage amplifier
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Old 10th July 2019, 09:43 PM   #581
Mark Tillotson is offline Mark Tillotson
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What happens if you make C6 1000F - removing ripple from the bases of the cascode. Normally a cascode would be regulated anyway with a zener or LED to help reduce rail artifacts getting to it.
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Old 10th July 2019, 10:27 PM   #582
edbarx is offline edbarx  Malta
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According to LTSpice the input stage's current source is very stable. With these simulations I am getting only a 1uA variation in its output current which translates to 1/3000.

The only current path besides the input stage's current mirror is through the differential pair's bases. However, current has to pass in the opposite direction to what it should under ordinary conditions. If this is true, the only reasonable conclusion is the differential pair's base-collector capacitance. This capacitance is being partially charged and discharged as a result of the rails artifacts and hum.
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Old 11th July 2019, 06:32 AM   #583
edbarx is offline edbarx  Malta
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The mains hum, or better 100Hz buzz, can easily be seen in the attached screenshot. This was obtained by adding the cascode's emitter currents and subtracting the input stage's current source's Ic. Due to the negative sign of Ic, I had to use an addition. Nevertheless, this should be easily to grasp.

The amplitude of oscillations illustrated in the screenshot is the sum of base currents feeding into the differential pair's bases.

The golden question here is: Why am I getting a 100Hz signal superposed on the legitimate signal?
Attached Images
File Type: png 2019-07-11-081919_1366x718_scrot.png (114.1 KB, 103 views)
File Type: png 2019-07-11-084418_1366x718_scrot.png (112.7 KB, 109 views)
File Type: png 2019-07-11-085606_1366x718_scrot.png (111.1 KB, 92 views)

Last edited by edbarx; 11th July 2019 at 06:59 AM.
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Old 11th July 2019, 07:12 AM   #584
edbarx is offline edbarx  Malta
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The 30 minutes edit time expired. So, I will have to post here:

The second screenshot shows the difference between the cascodes' emitter currents and the current mirror's Ic. These almost cancel out. The green trace is the current mirror's Ic. The modulating mains buzz is clearly illustrated.

The third screenshot shows the difference between the cascode's Ics. There are spikes in synchrony with the start and end of smoothing capacitor charging.
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Old 11th July 2019, 03:19 PM   #585
edbarx is offline edbarx  Malta
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I have just discovered that with the differential inputs shorted together, the VAS does not work properly, and is heavily out of balance. This, unfortunately, invalidates all these latest simulations.

To Moderators:
I would greatly appreciate if a moderator with post deletion power removes my latest posts from post #575 onwards.

Thanks.
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Old 11th July 2019, 07:12 PM   #586
Mooly is offline Mooly  United Kingdom
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My attempts at a design of a 3 stage amplifier
Quote:
Originally Posted by edbarx View Post
To Moderators:
I would greatly appreciate if a moderator with post deletion power removes my latest posts from post #575 onwards.

Thanks.
I know you'll understand We don't normally edit threads/posts, particularly where replies have come in in response to content already posted.

A thread is like a timeline, it tells a story and so to delete posts isn't really fair on those who have replied or on those who are following.

Your thread shows the design processes at work... and that is what it is all about.
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Old 11th July 2019, 09:17 PM   #587
edbarx is offline edbarx  Malta
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All right, Mooly. No problem.
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Old 11th July 2019, 09:29 PM   #588
mjona is offline mjona  New Zealand
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As previously stated star earth schemes are not easy to implement. There is a brief article on this at https://www.edn.com/design/consumer/...off-the-ground.

Given the persistence of your problem it would be worth paying the money to get the full articles. I have run a Tian simulation test which shows you have ample phase and gain margins even if your Miller capacitor is reduced from 100 pF to 39-47 pF.

Such reduction is made possible because the closed loop gain is 56.55 which places the unity gain point at 244 kHz which is very low by most standards.

There is about 3dB of mound of base boost below 100Hz which is rather strange.

I have attached the symbols and connections for a Tian plot so you can do your own investigations on your latest update of the simulation.

To use this you have to replace the expression for Vout with -1/(1-1/(2*(I(Vi)@1*V(x)@2-V(x)@1*I(Vi)@2)+V(x)@1+I(Vi)@2)) by clicking on that header in the plot. I usually copy this and put it at a convenient space on the .asc file and change the status from SPICE directive to Comment.

Select the two cursor option and drag one to 0 dB using the side arrow keys for fine adjustment Do do likewise for the second cursor placing this as close as possible to -180 degrees. Read off the stability margins in the box at the bottom.
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File Type: png Tianplot.PNG (186.1 KB, 71 views)
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Old 11th July 2019, 09:31 PM   #589
mjona is offline mjona  New Zealand
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PS change all coupling capacitor values to 1 (Farad) just for test purposes.
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Old 12th July 2019, 07:35 AM   #590
edbarx is offline edbarx  Malta
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Pasting the given expression and pressing OK, displayed a dialog complaining: "Invalid @step resquest" and "This data does not contain steps".
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