One of the Top Solid-State CFA amp design

[AndriyOL]

Originally Posted by john_ellis

AN approach that seems to work is to limit the input stages to two gain stages only - e.g. input differential and differential, Darlington VAS stage, with triplet output stages. Global NFB with phase lead from the output works with RC phase lag on the outputs of the differential input stage, and VAS output stage. However there may still be some slight, damped, internal ringing, which can be completely cured by taking the compensation from the VAS stage to the feedback point instead of the output connection. The 20kHz may increase to about 0.01% but THD is around 0.002% at 1kHz, lower if the global approach is used.

What is your simulation show, will it work or Mjona is right in his experience?

[mjona]

Originally Posted by AndriyOL

What is your simulation show, will it work or Mjona is right in his experience?

What John has described is a fresh design approach so when you ask "will it work" does this mean an entirely new circuit or applying John's ideas to the present one?

I looked at compensation on the basis of not departing significantly from the Lazy Cat design and showed that adopting John's proposed method would not work in this particular instance due to the snag of an additional pole to the two that already existed in the Vas and the first transistor in driver stage also having some voltage gain.

The other option without going to a complete redesign would be to rearrange the output into the form of a three stage emitter follower -which eliminates the added frequency pole mentioned in my last post.

With these changes the circuit delivers a THD which is on a par with my most recent simulation.

I was under the impression you want to stick as closely as possible to the original Lazy Cat structure.

I have not posted the simulation as it is not clear now what your design aims are and this is beginning to look like a competition where the entrants do all the work and there is no final result.

[AndriyOL]

Originally Posted by mjona

What John has described is a fresh design approach so when you ask "will it work" does this mean an entirely new circuit or applying John's ideas to the present one?

I was under the impression you want to stick as closely as possible to the original Lazy Cat structure.
I have not posted the simulation as it is not clear now what your design aims are and this is beginning to look like a competition where the entrants do all the work and there is no final result.

Preferably accomodating John's approach with present circuit, however entirely new circuit won't be a harm to my aim) while it provides high frequency responce, low output impedance, high slew rate, simple schematic (for small pcb) and low distortion, which can be achived with CFA design.

I don't insist to stick as closely as possible to the original LC structure, I just don't want HF responce to be killed with inductive add-ons.
Also my aim is to use components I currently posses, however using mosfets in drivers stage might be beneficial.

[mjona]

Originally Posted by AndriyOL

Preferably accomodating John's approach with present circuit, however entirely new circuit won't be a harm to my aim) while it provides high frequency responce, low output impedance, high slew rate, simple schematic (for small pcb) and low distortion, which can be achived with CFA design.

I don't insist to stick as closely as possible to the original LC structure, I just don't want HF responce to be killed with inductive add-ons.
Also my aim is to use components I currently posses, however using mosfets in drivers stage might be beneficial.

Thanks for clarifying the flexibility with your design aims, I will post my EF 3 simulation later.

In regard to your comment about HF response being killed with inductive add-ons, any effect with audio would show up in the THD results for a 20 kHz sine wave test signal.

If the error result is neglible you can forget the idea of any impairment being due to inductive add-ons.

We don't listen to square wave test signals a 10 kHz one is used to see how well the feedback loop works - this will be at extreme high frequencies before a point where phase changes arise ahead of a drop in output level.

[AndriyOL]

Originally Posted by mjona

Thanks for clarifying the flexibility with your design aims, I will post my EF 3 simulation later.
In regard to your comment about HF response being killed with inductive add-ons, any effect with audio would show up in the THD results for a 20 kHz sine wave test signal.

Thanks for your kind support. I understand in some designs it's impossible to omit output coil as a safe margin with different load. What I wrote about add-ons is a preference only.

[john_ellis]

Here is a simulation (sorry for the poor quality) of my 100W design using global feedback compensation at just over 100W and clipping as simulated. 100W distortion at 20kHz is 0.0016%. Still to be build and verified, however, the previous version achieved 0.003% at 20kHz, measured. (FET means FET input stage.)

[AndriyOL]

Are you saying FETs are better is such design in the input stage? (Where is FET means?)

Miller compensation I'm using is not robust enough than to maintain stability. What do you think LC is using in FO modules to stabilize such amps?

[john_ellis]

Yes, I am referring to using FETs in the input stage. But I'm not saying they are better, necessarily. I use FETS so that I can have D.C. frequency response (no electrolytics in the feedback path nor any capacitors to cause distortion in the audio band). I have used BJT's too but they are better with A.C. coupling and feedback because of the bias currents needed. I have designed a bias compensating circuit for D.C. application but not tested it and suspect it may introduce a noise current, but that might only appear when the amplifier is disconnected from a preamp.

I'll have to take another look at the LC design to comment.

[Eva]

Hi AndriyOL, I took a fast read at the thread.
As I told in the emails, there is no way to make a "current feedback" input stage with balanced high impedance inputs.
In a "current feedback" input stage there are 2 input nets. One of the input nets is low impedance, the other is high impedance.
Implementing high impedance balanced inputs with a "current feedback" input stage requires a buffer stage:
a) Summing its output in form of current to the low impedance net. Non-inverting buffer.
b) Summing its output in form of voltage to the high impedance net. Inverting buffer.
(End of list.)

The whole point of current feedback inputs seems largely misunderstood in audio. Where is the extra "speed" coming from? It comes from eliminating one gain element from the feedback path, so propagation delay and phase shift are reduced, allowing for highest GBW for a choice of part types.

In high speed current-feedback op-amp design (where state of the art of linear amplification is currently expressed, not so much in audio), typically IN- input current goes straight (through input transistors acting as cascodes) to drive VAS. LTP phase shift and delay are eliminated from IN-. This can represent an improvement of 33%, as in 3 gain stages becoming 2 (counting output stage as 1 gain stage). These op-amps are available with GBW of over 100Mhz, made with transistors exhibiting unity gain FT as high as 8Ghz. These op-amps are often used for video signals.

For audio linear amplification, while it is certainly advantageous to increase GBW, the delay and phase shift associated with VAS and output stage can be an order of magnitude higher than what is gained by removing the delay and phase shift from half LTP. On the other hand, balanced inputs for simple amplifiers, or bridging, are trivial to make with LTP input stages.

What has to be understood about linear amplification is that:
- There is a logic to derive the circuits. There is a logic that describes the few optimum possible circuits. This is Abstract Algebra.
- There is a physical limit to the performance that can be obtained for every set of part types, and amount of each part, chosen.
- When increasing the amount of part types, or the amount of each part, the slope of the function "measured_results(n_types,n_parts)" starts positive but becomes zero, then negative. Past a certain point, more parts are loss, best part types are already into use, the right amount too.
- Previous principle is also true for semiconductor design and production. Materials have a theoretical limit. The limit was reached.

[mjona]

I have never used FET's in amplifier input stages - to match pairs from single devices -say for an LTP - one might need a dozen or more samples.

Dual FET's on the same chip are a solution but you might need to put in a special order and be prepared to pay at a premium.

I am not against FET's per se.

Recently I saw a Conrad Johnson Sonographe CD player for sale in a shop and bought it on the spot.

This is a dressed up version of a 14 bit Phillips/Magnavox CD350 player which was the first player I ever bought.

It the CJ has wooden cheeks and a fancy front panel but inside there is a special board with a single FET replacing the final filter stage.

What a difference this makes.