Well, I think I can touch upon the question I see as most important. The drain-gate capacitance causes a varying voltage on the drain to add positive charge to the gate when it is increased and vice versa. Suppose the mosfet is connected with an open gate, starting with 0 charge with respect to the source, to a turned-off power supply with high current output capability, drain to + and source to -. When the power supply is switched on, the gate will be pulled high and the mosfet will be destroyed.
C vs V
In a power fet there is the body diode, a byproduct of its construction, between source and drain. This is reverse - biased in normal operation. Electrons trying to flow from the P layer are repelled by the electrons in the N doping of the N layer. This forms a "depletion" region of zero electrons, therefore no current can flow. The N and P layers are conductive, forming the plates of a capacitor, with the depletion region forming the dielectric. The ammount by which the electrons repel each other depends on the applied voltage, so the thickness of the depletion region depends on the applied voltage, and the thickness of the dielectric of the capacitor depends on the applied voltage. The result of which is that Cds varies with applied voltage., decreasing as the voltage is increased. The other capacitances vary in similar fashion, even if the mechanisms are different.
So that is why ( if I remember correctly)
For actual values, data sheets will probably provide graphs of capacitance versus voltage for the fet you intend to use.
Hope this is the answer to the question I thought you asked.
In a power fet there is the body diode, a byproduct of its construction, between source and drain. This is reverse - biased in normal operation. Electrons trying to flow from the P layer are repelled by the electrons in the N doping of the N layer. This forms a "depletion" region of zero electrons, therefore no current can flow. The N and P layers are conductive, forming the plates of a capacitor, with the depletion region forming the dielectric. The ammount by which the electrons repel each other depends on the applied voltage, so the thickness of the depletion region depends on the applied voltage, and the thickness of the dielectric of the capacitor depends on the applied voltage. The result of which is that Cds varies with applied voltage., decreasing as the voltage is increased. The other capacitances vary in similar fashion, even if the mechanisms are different.
So that is why ( if I remember correctly)
For actual values, data sheets will probably provide graphs of capacitance versus voltage for the fet you intend to use.
Hope this is the answer to the question I thought you asked.
I thought of adding a rather technical point about my example, revisiting it once again. When the power supply is increased, the charge on the gate is not actually increased, assuming it is electrically isolated in an open state, but its voltage nonetheless increases since internal capacitances decrease with increasing voltage. Varactor diodes seem to have the same effect, the result being similar to physically increasing the separation between two capacitor plates, but really being due to the diode nature johnnyx mentioned.
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