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Meridian 103 clone
Meridian 103 clone
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Old 20th March 2017, 08:45 PM   #21
sgrossklass is offline sgrossklass  Germany
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Try .STEPping your C5 and C6, can't be anything else really.

Hint: Use a Kaiser-Bessel windows with Beta=20 for your FFT.
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Old 20th March 2017, 10:08 PM   #22
RCruz is offline RCruz  Switzerland
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Thank you for the tip
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Old 21st March 2017, 07:50 AM   #23
AndrewT is offline AndrewT  Scotland
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Note that C5 has a -ve voltage applied to it's top end (next to R7) and that C6 has a +ve voltage applied to it's bottom end. Orient these caps to suit the quiescent voltage.
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Old 21st March 2017, 09:08 AM   #24
RCruz is offline RCruz  Switzerland
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It is C3 that controls LF roll off... with 500u the response seems much more linear
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Old 21st March 2017, 01:18 PM   #25
RCruz is offline RCruz  Switzerland
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Now that I have a working simulation I will try to analyse the circuit. (Here I do welcome specialist guidance).

Input transistors bases are connected together and referenced to GND so biasing is done by the bootstraps that feed the emitters of the input bgt.

For the negative pnp Q2 we have R9 and R10 bootstrap that feeds a voltage to Q2 emitter trough current limiting R12.
D2 seems to be used to compensate for temp variations on IPS.

For the positive npn Q1 we have the same arrangement trough R14 R15 R16 and D4.
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Old 21st March 2017, 01:23 PM   #26
RCruz is offline RCruz  Switzerland
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Feedback from the output is injected directly in the input.

Voltage divider R5 and R4 defines quantity, C3 isolates the circuit for DC and the current limiting R6 (18k) is bypassed by the compensation capacitor.
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Old 21st March 2017, 01:32 PM   #27
RCruz is offline RCruz  Switzerland
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IPS transistors are wired as common emitters so they provide voltage amplification with phase inversion. Gain is set by the ratio between collector and emitter resistors (R7 and R8 in the positive side).

For the positive side Q1, amplified signal comes from the collector that enters the base of Q3 (another common emitter).

Then follows a cascode Q6 that feeds the mirror responsible by transmiting the current to the voltage spreader that sets bias on the OPS.

The OPS uses medium power bjt for driving the output lateral mosfets.
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Old 21st March 2017, 01:36 PM   #28
RCruz is offline RCruz  Switzerland
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The voltage spreader (R23 R24 R31 Q10) is referenced to GND by the R22 R32 C7 and C8 circuit.
I did sim it without this GND reference and distortion whent up ... I am not sure how this circuit works.
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Old 21st March 2017, 01:38 PM   #29
RCruz is offline RCruz  Switzerland
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Apart from the output zobel we have also the two zobels R45 C12 and R46 C13 that are used to avoid excitation of the mirror elements.

In the input we have another zobel R3 C1 that might be there to avoid issues with interactions with input cables..... not clear.
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Old 21st March 2017, 01:40 PM   #30
RCruz is offline RCruz  Switzerland
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R1 + R2 set input impedance and R1 C2 form a low pass input filter.
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