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Need help in finding stability margins/loop stability in LTspice for my amp
Need help in finding stability margins/loop stability in LTspice for my amp
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Old 25th November 2013, 06:35 PM   #1
maouna is offline maouna  Greece
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Default Need help in finding stability margins/loop stability in LTspice for my amp

Hello. i am having difficulties in finding phase and gain margin for the amp below.i dont have any problems when finding stability margins for differential input amps but with this singleton input i cant evaluate it on lt spice.maybe its due to the topology used?? can anyone help? Ltspice file is attached.
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Last edited by maouna; 25th November 2013 at 06:43 PM.
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Old 27th November 2013, 09:45 AM   #2
maouna is offline maouna  Greece
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in differential input amplifiers ,i dont have any problem in simulating loop gain,but with this topology i cant....
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Old 8th December 2013, 06:05 PM   #3
maouna is offline maouna  Greece
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any idea?
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Old 8th December 2013, 10:35 PM   #4
Dave Zan is online now Dave Zan  Australia
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Quote:
Originally Posted by maouna View Post
... anyone help? Ltspice file is attached.
Put a Tian probe on the base of the VAS transistor. After the C1 connection.
This will reveal any instability, actually more correct than the usual methods.

Best wishes
David
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Old 8th December 2013, 11:13 PM   #5
jcx is offline jcx  United States
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its most portable to place any external transistor .model statements directly on the schematic with the Spice directive tool (far right)
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Old 9th December 2013, 03:10 PM   #6
maouna is offline maouna  Greece
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Quote:
Put a Tian probe on the base of the VAS transistor. After the C1 connection.
This will reveal any instability, actually more correct than the usual methods.

Best wishes
David
i will try and report

Quote:
its most portable to place any external transistor .model statements directly on the schematic with the Spice directive tool (far right)
i will repost .asc file with models on the schematic
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Old 9th December 2013, 03:19 PM   #7
matze is offline matze  Europe
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The problem is that there are two feedback paths: one DC for setting the operating point (via R3+Trimmer), and one AC via R10. For AC, both paths are coupled via C3.
One can connect the right-hand sides of R10 and R3, and place the probe between this junction and node A.

Additionally, the input AC voltage source Vin has to be turned of, when feeding the circuit from the gain probe. (it was on!)

Result is OK, ULGF around 300 kHz, phase margin 90 degrees.

Best regards,
Matthias
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Old 9th December 2013, 04:10 PM   #8
maouna is offline maouna  Greece
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Join Date: Oct 2008
Quote:
The problem is that there are two feedback paths: one DC for setting the operating point (via R3+Trimmer), and one AC via R10. For AC, both paths are coupled via C3.
One can connect the right-hand sides of R10 and R3, and place the probe between this junction and node A.

Additionally, the input AC voltage source Vin has to be turned of, when feeding the circuit from the gain probe. (it was on!)

Result is OK, ULGF around 300 kHz, phase margin 90 degrees.

Best regards,
Matthias
the other thing i tried to do last night was to connect the probe between the junction of R20_Trimmer and C3, and Q2's emitter. the results acquired this way were quite logical although i dnt know if the method i used was correct. i will come up with schematics to show you my findings.
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Old 9th December 2013, 04:20 PM   #9
maouna is offline maouna  Greece
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These were the loop gain results using Tian's loop gain probe.
The results claim 43dB Gain margin and 86 degrees Phase margin but i dont know whether these results are accurate enough or not.
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Old 9th December 2013, 04:57 PM   #10
matze is offline matze  Europe
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Quote:
Originally Posted by maouna View Post
These were the loop gain results using Tian's loop gain probe.
The results claim 43dB Gain margin and 86 degrees Phase margin but i dont know whether these results are accurate enough or not.
Hi,

these are the results I got with the other method.

BTW, the circuit contains a subtle problem. According to current terms, one could it call a simple non-symmetrical current-feedback amplifier (CFA), see the CFA threads.
The input impedance at its inverting input (emitter of input transistor) is quite low. I think, currently it is not much larger than the 150R resistor in the feedback network.

So, if you want to increase the loop gain by decreasing the closed-loop gain, you have to take care of the feedback network impedance and also of the coupling capacitor to the emitter of the first trannie.

Kind regards,
Matthias

PS. The way of setting AC 0 for the voltage source Vin is nice!

Last edited by matze; 9th December 2013 at 05:02 PM.
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