Has anyone seen this front-end before?

[Bonsai]

Hi Arthur,

The test was done with a load of 4 Ohms.
Whether 4 or 2 Ohms, it doesn't hardly make any difference.
Below the 'Bowes test' with 2 Ohms.

With a disabled TMC, the ringing was almost completely gone.

Cheers,
E.

edit: NB: Equally interesting (and important!) is the step response during the firing up phase.
See fig. 12q on my website.

Edmond, is that a loop stability problem or a local parasitics problem? Per my earlier post, there is a significant shift in device parameters with Vce and Vcb voltage swings. This btw is one of the mechanisms that causes ringinging when an amp comes out of sticky rail syndrome. Change the VAS transistor to something decent and use a Baker clamp and the problem is solved. No amount of loop compensation fiddling will fix the issue: it is local VAS instability that is the cause.

 

[Edmond Stuart]

Hi Andrew,

It's mostly a loop stability problem, caused by the sky rocketing Cgd of the power MOSFETs at low Vds. So a Baker clamp in the VAS won't help that much.

Cheers,
E.

 

[Edmond Stuart]

Hi Andrew,

I've repeated the 'Bowes test' with an ideal OPS (a VCVS) and the ringing was gone.
So it's definitely an instability issue of the OPS.

Cheers,
E.

 

[Waly]

As always with so called 'new' circuits, most details -or sometimes every detail- in isolation or partly in combination, were already know and published. This also appears to be the case with the SuperTIS. That's nice, because it reinforces my believe that it will work in real life too.

True, the only problem is your (in)ability to quote previous work. But don't worry, you are not alone, there is another renowned designer here that has the same modus operandi.

BTW, those circuits are not mine, so please stop quoting me.

The last problem you have to address before even thinking about an implementation is the chronic instability of the OPS in your autobias circuit. Hint: like it or not, there is a good reason why the LT1166 (that you so nicely emulated by extracting the essentials from the detailed device level schematic reverse engineered by somebody else and posted here) has the unity loop gain frequency of about 600KHz.

 

[PB2]

True, the only problem is your (in)ability to quote previous work. But don't worry, you are not alone, there is another renowned designer here that has the same modus operandi.

BTW, those circuits are not mine, so please stop quoting me.

The last problem you have to address before even thinking about an implementation is the chronic instability of the OPS in your autobias circuit. Hint: like it or not, there is a good reason why the LT1166 (that you so nicely emulated by extracting the essentials from the detailed device level schematic reverse engineered by somebody else and posted here) has the unity loop gain frequency of about 600KHz.

Do you have trouble reading or comprehending the title of this thread? "Has anyone seen this front-end before? " It seems that Edmond started right out by looking for prior work, so what are you all bent out of shape about?

Why don't you show us one of your novel designs if this bothers you so much?

It is actually nice to see and discuss something new even if it is built on prior work, this is usually how it goes anyway.

 

[PB2]

Have you built any of Edmond's ideas to confirm they are more than theoretical speculations, based purely on simulations using models of an unknown quality, and with ideally matched devices?

Do you truely believe that most of us are unaware of model quality, ideal matching, etc. such that you have to make a comment like this? I actually find it amusing that you think you have to inform us! Are you MK's best buddy?

 

[Bonsai]

Under steady state low signal level conditions the amplifier is stable. At high output swing levels, the parameters (in this case OPS devices, in other designs the problem is with the VAS devices) change significantly enough to cause the amp to exhibit instability at the signal peaks. Maybe parasitic is the the wrong term, but this is not sustained oscillation (PSIO - Parameteric Shift Induced Oscillation ;-)

The Baker clamp is not the cure agreed and I should have explained more clearly. But, if the VAS is suffering from sticky rail syndrome, it always exacerbates the ringing problem as the signal recovers. Worst I have seen is MJE340/350 when used as VAS - Cob is high and they have significant base storage issues in this role.

 

[PHEONIX]

Hello Guys,

This ringing near the rails how serious a problem is it, apart from the ringing is it a problem that we can live with or do we need to get rid of it because it has a failure mode that can effect the reliability of the amp. Is it an EMC issue.

I think that a possible solution would be to reduce the order of the compensation of the amp to first order as you get near the rail voltages at the output ( i dont know how you would do this) . My experience has been that the higher the order of amplifier compensation the greater the magnitude of this ringing is.

Regards
Arthur

 

[Edmond Stuart]

True, the only problem is your (in)ability to quote previous work. But don't worry, you are not alone, there is another renowned designer here that has the same modus operandi.

Walter/Waly/YWN
Now that Pete has quoted you, I can't pretend to not heaving read your comment.
Regarding previous work,
1. Read to references on my website. Of course it's not complete, as it is impossible to know of every amp once built and/or published.
2. Precisely for this reason I have opened this thread to learn more about prior art.

BTW, those circuits are not mine, so please stop quoting me.

If you don't like it, just stop commenting on this thread. What about that?

The last problem you have to address before even thinking about an implementation is the chronic instability of the OPS in your autobias circuit.

What about the 'chronic instability' of your simulator?
We all know about this embarrassing attempt to simulate distortion.

Hint: like it or not, there is a good reason why the LT1166 (that you so nicely emulated by extracting the essentials from the detailed device level schematic reverse engineered by somebody else and posted here) has the unity loop gain frequency of about 600KHz.

Thank you so much for your hint.
1.The ULGF of 600kHz is precisely the reason why this IC didn't catch up in the market. This chip is unsuitable for high-end amps, as the frequency compensation (when using pin-2) is ill-conceived.
2. The ULGF of Bob Cordell's HEC OPS is 3MHz and the PM around 90 degrees. AFAIK, this OPS does not oscillate.
3. The ULGF and PM of my AB2-OPS are the same as above, so if you encounter a 'chronic instability', that says more about the way you have simulated it, than about the AB2-OPS itself.

Do you have trouble reading or comprehending the title of this thread? "Has anyone seen this front-end before? " It seems that Edmond started right out by looking for prior work, so what are you all bent out of shape about?

Why don't you show us one of your novel designs if this bothers you so much?

It is actually nice to see and discuss something new even if it is built on prior work, this is usually how it goes anyway.

Thx for your comment, Pete.

Cheers,
E.

 

[Edmond Stuart]

amusing

Do you truely believe that most of us are unaware of model quality, ideal matching, etc. such that you have to make a comment like this? I actually find it amusing that you think you have to inform us! Are you MK's best buddy?

Hi Pete,

Not just amusing, but also insulting.
Or do you mean an amusing example of self-projection?

Cheers,
E.

 

[Edmond Stuart]

ringing

[..]
The Baker clamp is not the cure agreed and I should have explained more clearly. But, if the VAS is suffering from sticky rail syndrome, it always exacerbates the ringing problem as the signal recovers. Worst I have seen is MJE340/350 when used as VAS - Cob is high and they have significant base storage issues in this role.

Hi Andrew,

As a matter of fact, the TIS does suffer from a tiny bit of sticking. Maybe it also contributes to the ringing. I have to check it out. If so, I'll add a Baker clamp.

Cheers,
E.

edit: Indeed, a Baker clamp helps a bit. The amplitude of ringing becomes about 50% smaller.
Now, I have to figure out a clamp that doesn't contribute to distortion.

 

[Edmond Stuart]

Baker clamp

See below for the effect of the Baker clamp on ringing.
Indeed it does help.

Cheers,
E.

 

[AndrewT]

Is this the square wave superimposed on the high level sinewave at the peak sinewave level?

 

[Edmond Stuart]

Yes.

 

[Edmond Stuart]

ringing

Hello Guys,

This ringing near the rails how serious a problem is it, apart from the ringing is it a problem that we can live with or do we need to get rid of it because it has a failure mode that can effect the reliability of the amp. Is it an EMC issue.

Hi Arthur,

If the ringing at low Vds doesn't escalate, I can live it. At (near) clipping levels the signal is already distorted anyhow.

I think that a possible solution would be to reduce the order of the compensation of the amp to first order as you get near the rail voltages at the output ( i don't know how you would do this) . My experience has been that the higher the order of amplifier compensation the greater the magnitude of this ringing is.

Regards
Arthur

You're right, the lower the order of compensation, the less ringing. But I also don't know how to dynamically reduce the order.

BTW, using MOSFETs with a lower Cgd will also help, as well as lower gate stoppers. As for the latter, I don't know yet what's the lowest permissible value is without provoking another kind of instability. This is typically something that has to be figured out in real life.

Cheers,
E.

 

[PHEONIX]

See below for the effect of the Baker clamp on ringing.
Indeed it does help.

Cheers,
E.

Hello Edmond
Can you post TIS circuit with baker clamp that resulted in these implementation.

Regards
Arthur

 

[Edmond Stuart]

Baker clamp

Hi Arthur,

Sure. See: V4, V5, D1...D4, R15, R15, R18, R19, R33 & R34.
To do: Finding suitable Zeners for V4 & V5 and checking the clamp loop gain & phase.

Cheers,
E.

 

[R Dijk]

Hi Ronny,

Nothing wrong with a CMCL, but I rather prefer an apples to apples comparison (thus without using a CMCL).
In this respect the circuit you have put here would have been more appropriate. But again, THD20K of that circuit is much more higher. Probably, (partly) due to the local feedback via R89 and R91. However, when I disabled the local feedback, the VASes start a fierce fight, resulting in an enormous distortion. Apparently it's caused by unequal gains of the LTPs (or VASes?). With C9 = 85pF and C10 = 115pF the fighting has almost gone. It also has gone when I replaced the Miller compensation by an 'input inclusive compensation' (by means of only one capacitor, though in that case you also need extra lead-lag compensations between the drains of the jfets).

BTW, are you sure your latest schematic is correct? It doesn't work according my simulation (I got a huge distortion; fighting VASes again?).

Cheers,
E.

Hi Edmond do you mind comment on more current gain in the vas stage as an alternative to an extra stage in the amplifier ?

Yes there vas some fighting issues in that stage.

 

[Edmond Stuart]

Hi Ronny,

It's an interesting idea. At first sight I can't judge about it, of course.
Tomorrow (it's too late now) , I will also sim your circuit.

Cheers,
E.

 

[PB2]

Hi Pete,

Not just amusing, but also insulting.
Or do you mean an amusing example of self-projection?

Cheers,
E.

I can understand how you might feel insulted but that would only be if you took them seriously. You came in and asked point blank for references to prior work so I have a hard time taking their comments seriously. The amusing part is how they accuse you of wanting attention, when their comments are simply to draw attention to themselves. I suppose yes, self projection.