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Old 29th January 2015, 11:27 PM   #5001
Bob Cordell is offline Bob Cordell  United States
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Quote:
Originally Posted by Alan0354 View Post
What do you mean by sensitive? Say if I set for 10mA, how much would I expect to change? Seems like if too much imbalance in current, the 47K resistor can be reduced to lessen the effect. Say even down to 10K, it's still higher than if you resort to resistor load of the IPS.
Exactly.

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Bob
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Old 29th January 2015, 11:27 PM   #5002
Alan0354 is offline Alan0354  United States
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Originally Posted by Ranchu32 View Post
Well I hope it works; I'll find out soon enough, my boards will arrive any day now.
Sorry to ask question on Mr. Cordell's thread.

But your schematic and the transistors you picked is very similar to my design. I have a few questions:

1) I use KSA992 and KSC1845 for all the front end transistors. You use BC550 and BC560. Any particular reason? I did look into this also, but I ended up using one pair for all the small signal transistors because I like the low Cob that implies lower capacitance on the others.

2) what is the advantage of using Q21 and Q22 combined for the Vbe multiplier? I use KSC1845 alone and mount it onto the heat sink.

3) I use 3EF for OPS, but I use all NPN and PNP on one side to keep it simple.

I just want to hear your thinking.
Thanks
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Old 29th January 2015, 11:37 PM   #5003
Bob Cordell is offline Bob Cordell  United States
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Originally Posted by Alan0354 View Post
Thank you very much Mr. Cordell. I designed for 10mA through the VAS, It does not matter whether it is 15mA or 5mA(+/-5mA). I think I have it covered. I used KSA1381 and KSC3503 with 50V max rail. I think I can take the variation.

Just for curiosity, I use 300ohm for emitter degeneration for all 4 of the transistors of both differential pair. Does that help a lot on the balance? I run 2mA tail current for each LTP.

Thanks
I believe that the current mirrors should always be degenerated with emitter resistors. I generally go for about 10:1 degeneration, meaning that RE is about 10X re of the transistor. A transistor running 1mA would thus have an RE of about 260 ohms.

The amount of degeneration in the current mirror also affects the noise contribution of the current mirror, with smaller RE causing a higher noise contribution.

Finally, in the complementary arrangement with the current mirror shunt resistors, note that the choice of the value of the current mirror emitter resistors is inter-twined with the choice of the tail current and amount of degeneration in the VAS emitter circuit.

Cheers,
Bob
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Old 30th January 2015, 02:00 AM   #5004
Alan0354 is offline Alan0354  United States
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Originally Posted by nattawa View Post
I think I saw VAS current change of 2-3 mA, and that was by Hfe mismatching at one pair of transistor alone, before any Vbe mismatching and temperature stepping simulation that I didn't bother trying.

Yes, you can reduce the load resistor but that would further negates the point of using a current mirror.
I gave it some thoughts, seems like the degeneration of both the differential transistors and the transistors in the current mirror is the KEY for matching. Notice I use 1K to degenerate the current mirror transistors. This will drop 1V across the resistor. This will more than swamp out the Vbe difference. I use 300ohm degeneration for the differential transistor, that's 300mV.

I don't know why you think it's so important about hfe matching as any imbalance in current will be compensated by the action of the degeneration resistors. There is no other way around it. It's like when one transistor tries to pull more current, the voltage drop over the emitter resistor literally FORCE the other transistor to conduct more to fight for the constant current!!!!

To me, the difference in Vbe between the two transistors of the differential pair and the current mirror is even more important than the hfe if you have plenty of degeneration. That's the reason I sacrifice 1V of headroom and use 1K on the current mirror, sacrificing gain of the IPS and use high value degeneration resistor to overcome the matching problem.

These are all common sense theory, not relying on simulation. You design to force the circuit to match. Then I use 2EF on the VAS to up the input impedance to get back the gain at LF. Then make the VAS a current integrator at HF as Mr. Cordell described so nicely.

Last edited by Alan0354; 30th January 2015 at 02:04 AM.
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Old 30th January 2015, 02:40 AM   #5005
Ranchu32 is offline Ranchu32  Australia
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Quote:
Originally Posted by Alan0354 View Post
Sorry to ask question on Mr. Cordell's thread.

But your schematic and the transistors you picked is very similar to my design. I have a few questions:

1) I use KSA992 and KSC1845 for all the front end transistors. You use BC550 and BC560. Any particular reason? I did look into this also, but I ended up using one pair for all the small signal transistors because I like the low Cob that implies lower capacitance on the others.

2) what is the advantage of using Q21 and Q22 combined for the Vbe multiplier? I use KSC1845 alone and mount it onto the heat sink.

3) I use 3EF for OPS, but I use all NPN and PNP on one side to keep it simple.

I just want to hear your thinking.
Thanks
Hi Alan

I'm keen to see your circuit.

I chose the high gain, low noise BC5x0 transistors for the complementary LTPs because I believe these parameters make them ideally suited for this application. High Vce transistors such as the KSA992/KSC1845 tend to be compromise these important parameters to achieve higher breakdown voltages.

I could have used the BC5x0 in the LTP cascade positions also, since the rail voltage specified are within their limits; however, I wanted to be able to scale the design at a future point with minimal changes.

Q21 and Q22 make up the CFP bias spreader; the high gain is useful with symmetrical voltage gain stages where the bias voltage is indeterminate. Q21 is a TO-126 package fixed to one of the output transistors, the other is a free-standing TO-92.

The benefit of this particular EF3 topology is that the driver and pre-driver temp co's cancel, simplifying thermal compensation. The other benefit is that the pre-drivers are bootstrapped to the output and pass only the bias voltage; high gain small signal transistors can be used where other topologies would call for parts with higher breakdown voltages and lower gain.

All this is covered in Bob's wonderful book.

Last edited by Ranchu32; 30th January 2015 at 02:46 AM.
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Old 30th January 2015, 03:53 AM   #5006
nattawa is offline nattawa  Canada
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Quote:
Originally Posted by Alan0354 View Post
I gave it some thoughts, seems like the degeneration of both the differential transistors and the transistors in the current mirror is the KEY for matching. Notice I use 1K to degenerate the current mirror transistors. This will drop 1V across the resistor. This will more than swamp out the Vbe difference. I use 300ohm degeneration for the differential transistor, that's 300mV.

I don't know why you think it's so important about hfe matching as any imbalance in current will be compensated by the action of the degeneration resistors. There is no other way around it. It's like when one transistor tries to pull more current, the voltage drop over the emitter resistor literally FORCE the other transistor to conduct more to fight for the constant current!!!!

To me, the difference in Vbe between the two transistors of the differential pair and the current mirror is even more important than the hfe if you have plenty of degeneration. That's the reason I sacrifice 1V of headroom and use 1K on the current mirror, sacrificing gain of the IPS and use high value degeneration resistor to overcome the matching problem.

These are all common sense theory, not relying on simulation. You design to force the circuit to match. Then I use 2EF on the VAS to up the input impedance to get back the gain at LF. Then make the VAS a current integrator at HF as Mr. Cordell described so nicely.
To my understanding, in a full complementary IPS-VAS such as Bob's Fig. 7.10, a "fight" of forcing balance component mismatching, due to ambient temperature rise for example, always ends up altering VAS current. This is very different from a single-ended VAS loaded with a constant current source scenario. The more close you match the devices, the more you can anticipate the match over a certain temperature span, in turn the likely less VAS current variation consequence. I think this is what's behind the device matching, and the reason I chose to use dual transistors as the input pairs and current mirror transistors. I have little clue how much the matching would matter so I do best I can in matching.

Ranchu32's Vbe multiplier can handle large VAS current variation, and it may help ease up the matching concern somewhat.
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Old 30th January 2015, 03:53 AM   #5007
Alan0354 is offline Alan0354  United States
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Originally Posted by Ranchu32 View Post
Hi Alan

I'm keen to see your circuit.

I chose the high gain, low noise BC5x0 transistors for the complementary LTPs because I believe these parameters make them ideally suited for this application. High Vce transistors such as the KSA992/KSC1845 tend to be compromise these important parameters to achieve higher breakdown voltages.

I could have used the BC5x0 in the LTP cascade positions also, since the rail voltage specified are within their limits; however, I wanted to be able to scale the design at a future point with minimal changes.

Q21 and Q22 make up the CFP bias spreader; the high gain is useful with symmetrical voltage gain stages where the bias voltage is indeterminate. Q21 is a TO-126 package fixed to one of the output transistors, the other is a free-standing TO-92.

The benefit of this particular EF3 topology is that the driver and pre-driver temp co's cancel, simplifying thermal compensation. The other benefit is that the pre-drivers are bootstrapped to the output and pass only the bias voltage; high gain small signal transistors can be used where other topologies would call for parts with higher breakdown voltages and lower gain.

All this is covered in Bob's wonderful book.
Thank you. More for me to think about. You might cost me a day or two!!!
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Old 30th January 2015, 08:46 AM   #5008
Edmond Stuart is offline Edmond Stuart  Netherlands
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Default Pick your poison

Hi Bob,

Quote:
Originally Posted by Bob Cordell View Post
[...]
Your circuit solution to this problem is quite brilliant, and very effective,
Thank you!
Quote:
but a bit more complex than some would choose. We pick our poison :-).
Cheers,
Bob
Apart from the the superior performance, a full-blown version of the SuperTIS (fig. 6 on my website), is a bit less complex then Alan's implementation of fig. 7.10 and equally complex as the front-end of your HEC amp.
In addition, as the standing TIS current of fig. 7.10 isn't rock stable, one need a better (read more complex) bias circuit for the OPS.

Cheers, E.
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Old 30th January 2015, 08:55 AM   #5009
mcd99 is offline mcd99  United Kingdom
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Quote:
Originally Posted by Alan0354 View Post
I looked at the schematic for a minute. I don't get what he is doing. But I don't see there is any current setting mechanism.
Edmond's SuperTis front end is a very clever and elegant design. Have built a simplified version and it works very nicely. It balances (biases) perfectly as long as thermal issues are taken into account. It is a good way of getting the benefits of a VAS common mode control loop but without additional complexity.

Paul
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Old 30th January 2015, 08:58 AM   #5010
Edmond Stuart is offline Edmond Stuart  Netherlands
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Quote:
Originally Posted by Alan0354 View Post
It does not have the resistor to set the current like in Fig. 7.10. I am not going to spend the time and change to a totally different circuit.
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Originally Posted by Alan0354 View Post
Which part of my question SPECIFICALLY asking about Fig. 7.10 DON'T YOU UNDERSTAND?
Your are barking up the wrong tree. As far as I can remember, I've never asked you to look at my circuits. Someone else did that.
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