Why am I getting a positive phase shift

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Hi, new at the forum taking up an old interest.
Spending my xmas holidays sorting a shoe box full of old circuit sketches.
Also, came across the TopSpice simulator which I downloaded and just for fun tried out on some of my old circuits.

This one I have problem with. Can't understand what is causing the positive phase shift making it an 25 Mhz oscillator. Don't mind the (missing) details, just look at the idea. Neither mind the component choise, it is what I had to play with in the demo version.

Q3 and Q4 is a standard diff amp. The load, Q6 and Q7 is a standard current mirror leaving ( / taking) its excess current into Q9 and further into Q10 for amplification. Since Q10 and Q11 share a current source, the R5 will create a voltage swing for the output, from the current swing in Q10.
 

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is compensation one of the missing circuit details?

I really wouldn't expect that many cascaded gain stages to stable without explicit Cdom

also never start with .AC analysis - always demonstrate that a realistic operating point has been found with a .TRAN and "debug" based on .TRAN circuit values
 
If you follow the signal through, the out put is inverted (180 degrees) from the non inverting input. the signal is inverted at the collector of q3, the non inverte4d at the collector of q9 and emitter of q10, then inverted at the output stages. Many ways to correct this - I would reverse the current mirror on the input. Also, as mentioned, no compensation.
 
Thanks for your idea to reverse the current mirror, but sorry, the same result.

Compensating, yes, but how? Since my positive phase appears already at about 50kHz a compensation had to start at a redicously low frequency. So to really know where to compensate, my question "why" is still valid.

There are of course plenty other methods to create the voltage swing, but this caught my interest since it gives a really nice transient answer, due to the current controlled current amplification.
 
I don't know where the positive shift comes from, but maybe you can stabilize it with a capacitor between collector of Q11 and base of Q9 to set the dominant pole. Something like 100pF - maybe more.

There's huge open-loop gain in that circuit though, so it could be hard to tame.

Emitter resistors for Q3 and Q4 (say 100R each) would help a few things:
a) Better input-stage linearity.
b) Higher open-loop input impedance.
c) Allows you to reduce the compensation capacitor mentioned above at least 10-fold (maybe to 10pF), giving much better slew rate.

btw: Why are R11 and R12 mismatched?

Also: R11, R12 and R13 probably have nasty effects at HF. Reducing or getting rid of them might help.

To get a better idea of what's going on, try modeling it open-loop i.e. with the feedback disconnected.
 
Thanks godfrey, the Q3, Q4 emitter resistors did the trick. Do you know why ? Always nice to learn the reasons behind. Maybe there wouldn't have been a problem if I had used a real current source (with limited input impedance) instead of the ideal one. I will test this to but then I have to use another SPICE copy. I have downloaded the LT Spice and it seems a lot better, allowing me to use zener diods too.

The R11 , R12 mismatch is due to the fact that a current mirror is not totally symmetric and the resistanse diff is needed to zero-bias the output. In reality there is a pot there to trim the output offset (typical solution).

As mentioned initially this was just a principal solution. Maybe I will use it in my upcoming MOSFET power amp project. I am testing out a few different solutions for each stage.
 
The R11 , R12 mismatch is due to the fact that a current mirror is not totally symmetric and the resistance diff is needed to zero-bias the output. In reality there is a pot there to trim the output offset (typical solution).
The mirror's probably good enough. Most of the DC offset will be due to Q4's base current flowing through R14. If you use ac coupling e.g. as shown, then the voltage drops across the 39K resistors will match to some extent to improve DC offset. You need Q3 and Q4 to be fairly well matched, though.

Your 10mA LTP current looks quite high, especially with R14 = 39K. The voltage drop across R14 must be quite high - maybe a volt or so? Reducing the current and/or resistance would help the DC offset a lot. Remember even if you trim it right, it will drift with temperature.

I don't like the idea of trimming the mirror because that will change the gain as well, and also cause distortion - it's much better to adjust so Q3 and Q4 have equal collector currents. I included the 1K resistors as stupid-proofing in case the trimmer goes open-circuit.

The 100pF is not just for RF filtering. It's main job is to keep Q3's base at low impedance relative to earth at high frequencies, especially when nothing is connected at the input. Otherwise you risk oscillations again.

I'm off to the pub now for a quick one before closing time :cheers:
Will post about the HF stuff later (sobriety permitting) or tomorrow.
 

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Yes you are probably right about the mirror and the base current on Q4. The 10 mA was not intentional, just left there since earlier simulations. Changed down to 2 mA. But the positive phase is still there.

Thanks for your effort, have one beer for me too. I'm headed for the sofa watching snooker on Eurosport.
 
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I agree with godfrey. You should probably try to simulate it without feedback first. The DC working point can be a bit tricky to get right though.

I see a similar issue when I simulate a KGSS headphone amplifier I am currently working on. With the loop closed, I get a small peak in the frequency response at around 3MHz and a positive phase with a peak of +50 degrees at around 6MHz. When I simulate it open loop I get a relatively low gain a these frequencies, but with a lot of phase shift, leading to an almost positive feedback.
 
Noted myself that adding a load on the output totally changed the situation. Now the transfer is more what one would expect.

Listening to some of your advices, and removing one current amplifier, the result is much better. Posting a new circuit, the frequency transfer and the step response of the current thru Q6 (with resistor R4 this corresponds to a near 20 V step in 20ns). Unfortunately the step is not that good after the FETs, but that is due to them solely (or?).

This rises some new questions. In the LTSpice model, the MOSFETs draw a lot of current on the gate (up to 0.5mA), not DC but when applying the signal source. How come? Does anyone know how where to find appropriate models for say 2SK1058 and 2SJ162? How do I add such a model ?
 

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Try IRF610 and IRF9610. If you don't have them I can give you models if you need them.

Also, you may want to put a diode in series with Q5's emitter. Normally Q3 has 0V Vcb which is unhealthy for a BJT.

The Q5/Q6 arrangement is very interesting:

1: Q5 has constant Vce, for better linearity.
2: Vce is high, near 40V, so Cob is very low and bandwidth is increased.

However, I don't think this is necessary. I think you would have the same performance if you just normally cascoded Q5 with a PNP on its emitter and drove the outputs from there.

Also, the MOSFETs each need about 4V of G-D bias to get them in their linear region and into class A.

If you're interested in adding 2 more BJT's you could do a Allison-type output stage with MOSFETs, which would perform very well and would bias itself with little hassle (that is if your output is supposed to be class A). I can help if you're interested.

- keantoken
 
keantoken, you caught my interest, what is an Allison-type output stage ?

I made a thread about it here:

http://www.diyaudio.com/forums/soli...veral-unique-allison-based-output-stages.html

The possibilities of the Allison are endless, so to keep from being incredibly vague I've attached what I had envisioned. The whole idea revolves around Q8 and Q7, which I call the Allison transistors. It is important that their emitters are joined and that they must share the same current.

I also might suggest the JLH output stage. It would integrate nicely with the circuit. Look at Tr1, 2 and 3 in figure 3.

http://www.tcaas.btinternet.co.uk/jlh1969.pdf

- keantoken
 

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Hi keantoken
In your Allison thread, the image in the first post won't expand :confused:, so it's hard to see what's going on.
If you have the image saved someplace, it would be great if you could repost it (here or there). Maybe one of the mods would be kind enough to replace the original pic in the Allison thread?
Cheers - Godfrey
 
... step response of the current thru Q6 (with resistor R4 this corresponds to a near 20 V step in 20ns). Unfortunately the step is not that good after the FETs, but that is due to them solely (or?).
The step response of the voltage on the collector of Q6 will be much slower than the current step through it. Mosfets have very high DC input impedance, but also a fair amount of input capacitance, so the current through Q6 has to charge and discharge this capacitance as well as driving R4. The voltage step at the output should be almost as fast as the voltage step at the collector of Q6.
... the MOSFETs draw a lot of current on the gate (up to 0.5mA), not DC but when applying the signal source. How come?
Same story. The higher the frequency, the higher the current needed to drive the gate capacitance.
 
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