JFET sorting by Ron?

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Tried a quick experiment that looked promising. Using test probes with clips and grabbing the gate and source with one and the drain with the other (so as not to heat the FET) and using the 200 Ohm scale on a handheld DVM I was able to get instant readings of the "0" Vds channel resistance. This in theory is the inverse of the gm at Idss which for constant process "beta" factor would directly indicate the Idss. I pulled out one half of a super matched pair and grabbed a FET from a totally different date code with and almost identical Ron, the amp retained a very low Vos.
 
scott wurcer said:
Tried a quick experiment that looked promising. Using test probes with clips and grabbing the gate and source with one and the drain with the other (so as not to heat the FET) and using the 200 Ohm scale on a handheld DVM I was able to get instant readings of the "0" Vds channel resistance. This in theory is the inverse of the gm at Idss which for constant process "beta" factor would directly indicate the Idss. I pulled out one half of a super matched pair and grabbed a FET from a totally different date code with and almost identical Ron, the amp retained a very low Vos.

Sure, that's perfectly fine for matching JFETs.

All handheld DVMs that I've seen are injecting a constant current in the DUT and measure the voltage across; for a typical 3 1/2 digit DVM, the current on the 200 ohm scale is 1mA.

You measured and compared the JFET linear region(s) where gm is exactly half the gm in saturation. That's perfectly fine, as far as Idss is much larger than the measuring current, which is fine for BL or V devices, could be a problem for GR devices. For GR devices, you may enter the quasi-saturation region (that is, the region where Id-Vds starts bending) and the matching process could be a little shaky.
 
EUVL said:
Thanks for the tipp.

Perhaps one question :

What is the advantage compared to measuring Idss with an ampmeter ?
It seems the effort is about the same ??


Patrick

You don't get any self heating, that is the measurement settles instantly and you don't need anything but the meter. I was having to wait for a while to let the curent settle in when measuring Idss.
 
Re: Re: JFET sorting by Ron?

syn08 said:


For GR devices, you may enter the quasi-saturation region (that is, the region where Id-Vds starts bending) and the matching process could be a little shaky.

The 2SK170 datasheet shows a min Idss of 2.6mA this would give a compliance burden of 50-60mV max @ 1mA, I would think the errors would remain minimal.

I'm curious what other folks consider an optimum match. Gm at the same operating point, Vos as a diff-pair at a particular operating point, untrimmed THD in a particular configuration?
 
I'm curious what other folks consider an optimum match.

Last thing I heared was at least 2 point transconductance measurement at IDSS or operating point.

Wether that is in any way effective in reducing distortion I was never given the chance to test, as nobody took the opportunity and sent me a pair of his good stuff.

Have fun, Hannes
 
Re: Re: Re: JFET sorting by Ron?

scott wurcer said:


The 2SK170 datasheet shows a min Idss of 2.6mA this would give a compliance burden of 50-60mV max @ 1mA, I would think the errors would remain minimal.

Scott; let me repeat.
For minimal errors you still need to supply your gate with about 25-30mV to compensate it's bias by 50-60mv on drain, but it is rather an academic question.
 
Re: Re: Re: Re: JFET sorting by Ron?

Wavebourn said:


Scott; let me repeat.
For minimal errors you still need to supply your gate with about 25-30mV to compensate it's bias by 50-60mv on drain, but it is rather an academic question.

Yes, but I am just thinking of a kind of equivalence of matching criterion where small details make an even smaller difference. But thanks for an idea, floating the gate with a couple of 1Meg resistors (D to G, G to S) like in the "distortionless" FET gain control circuit will do the trick nicely.

Patrick - Yes I was just wondering if the 0 bias on resistance correlates to the same percentage as Idss, trying to save some time.:)
 
Re: Re: Re: Re: Re: JFET sorting by Ron?

scott wurcer said:


Yes, but I am just thinking of a kind of equivalence of matching criterion where small details make an even smaller difference. But thanks for an idea, floating the gate with a couple of 1Meg resistors (D to G, G to S) like in the "distortionless" FET gain control circuit will do the trick nicely.

Patrick - Yes I was just wondering if the 0 bias on resistance correlates to the same percentage as Idss, trying to save some time.:)

It does indeed. Measuring resistance such a way I was getting FETs for my phasers, so all 8 of them will change resistance proportionally with a gate voltage. Such a way all APF's working in unison created closest dips in frequency response when thoroughly balancing output with input signals.
 
Scott;

can you suggest how to select bipolars for current mirrors? I need something like 10:1 devices. However, I can parallel them for "statistical matching", but I would like them to share the load more equally. Or is it not necessary? They are 2SC1815G devices, I want to mirror about 20 mA x 200 mA. They will be tightly coupled thermally by 2 copper strips, with an input one in the middle.
 
If you really wanted to try this you could parallel devices until the Vbe was about 60mV less at 20mA total than the single device, don't worry about the sharing. Then I would put about 250mV of degeneration in each side (this is about the point of diminishing rerturns). The result would probably be OK, but as you said it is a bit of inappropriate application of IC techniques to discrete design.
 
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