Better power MOSFET models in LTSpice

These are the 240/9240 models Cordell put in his last post. There are other models but this is the new VDMOS model which should do everything well. BUT, only a few people have seen it yet. So please verify it to your satisfaction (Cordell has the test jig and everything in his post) before using it for anything important.



PS. I didn't actually do much work, I just expressed enthusiasm mostly, hesitant to mess with the models because I knew I couldn't do better than Ian or Cordell and didn't see a way to help with the problems that were coming up. Now that the dust is settling a bit, I think I will try out the new model.

I simulated my CFA 200W amp with VDMOS ksubthres models and improvements are quite high(lower THD), specially with harmonic distribution and that at all output levels. Tat is very well visible at output level when the amp goes out of A Class, here is at 10 W/8 ohm.
Merry Xmas to all.
Damir
 

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What a pity ......
Works for depletion as well as enhancement ?

Perhaps the likes of DN2540, LND150, BSP149, ....


Patrick

I have never formally looked into it, but I suspect that JFETs also have subthreshold (sub-pinch-off) conduction, although it may not be of the exact same nature as that of MOSFETs.

In any case, I have tried the VDMOS kthres model on a lateral MOSFET, and it worked quite well. Interestingly, the subthreshold region in the lateral MOSFET extends into the reverse gate bias (depletion) region. This should be no surprize, since the threshold voltage of JFETs is usually quite low. So I think the answer is that the ksubthres model does work in the depletion mode as well.

Cheers,
Bob
 
I simulated my CFA 200W amp with VDMOS ksubthres models and improvements are quite high(lower THD), specially with harmonic distribution and that at all output levels. Tat is very well visible at output level when the amp goes out of A Class, here is at 10 W/8 ohm.
Merry Xmas to all.
Damir

These are very nice results. We are making good progress here.

Cheers,
Bob
 
I simulated my CFA 200W amp with VDMOS ksubthres models and improvements are quite high(lower THD), specially with harmonic distribution and that at all output levels. Tat is very well visible at output level when the amp goes out of A Class, here is at 10 W/8 ohm.
Merry Xmas to all.
Damir

Yes, this is to be expected. The spray of very high-order harmonics is due to the abruptness in the Gm of the old model due to not having subthreshold or not modeling it correctly. The addition of subthreshold conduction makes the Gm curve more gradual at low currents, which would be expected to reduce high order harmonics as well.
 
What a pity ......
Works for depletion as well as enhancement ?

Perhaps the likes of DN2540, LND150, BSP149, ....


Patrick

Yes, it works for depletion mode as well. Salas has a DN2540 model and there is also an LND150 model on the LTSpice Yahoo group, which could be updated with subthreshold conduction by someone who has some free time. There are newer IXYS depletion MOSFETs with Idss=15A or so that could be interesting too.
 
Okay guys, it would help if you could post links or attach datasheets or measurements with clear, precise plots of Gm and Id vs. Vgs. I got the IRF540 to model Gm within 1% above 3A, but below that the graph just doesn't have enough data and the digitizer can't extract it without significant errors.

Also, ST datasheet has different curves than the Fairchild datasheet which has different curves than the IR datasheet, etc etc. How do I choose which one to model? I guess it just depends on which datasheet gives the best data...
 

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I simulated my CFA 200W amp with VDMOS ksubthres models and improvements are quite high(lower THD), specially with harmonic distribution and that at all output levels. Tat is very well visible at output level when the amp goes out of A Class, here is at 10 W/8 ohm.
Merry Xmas to all.
Damir

I have almost same harmonic profile like yours (with and without ksubthres models). But THD rise with ksubthres models. My amp is VFA with Hitachi VAS.
 
If you were using an old NMOS/PMOS model, upgrading to VDMOS will result in higher distortion because the old models give much too low gate capacitance.

The Phillips datasheet for the IRF540 gives lots of detailed information, even a plot of the subthreshold region. The Phillips IRF540 is very similar to the Fairchild and most of other makers, so I think it will respresent most of the available devices. The ST IRF540 is something else with clearly different characteristics. I will try digitizing the Phillips datasheet later and using it for the model instead.
 
Okay guys, it would help if you could post links or attach datasheets or measurements with clear, precise plots of Gm and Id vs. Vgs. I got the IRF540 to model Gm within 1% above 3A, but below that the graph just doesn't have enough data and the digitizer can't extract it without significant errors.

Also, ST datasheet has different curves than the Fairchild datasheet which has different curves than the IR datasheet, etc etc. How do I choose which one to model? I guess it just depends on which datasheet gives the best data...

In general I've depended on measurements of actual power MOSFET devices to get models with decent performance at low current, especially for the subthreshold region. It doesn't take many datapoints in the subthreshold region to get what you need, because the exponential behavior there is fairly well understood. The subthreshold slope just needs to be inferred with some confidence. Vgs measurements at 10uA, 100uA, 1mA and 10mA is probably plenty. Vgs will usually change about 200-500mV per decade. I have found that a conventional VDMOS model that does a decent job of modeling above subthreshold can be made pretty accurate by just adding a value of ksubthres that just brings up the low-end current up to the proper subthreshold slope.

Cheers,
Bob
 
By coincidence I have been measuring IRFP240 and IRFP9240 FETs recently in the low current region (< 1A) and found them to behave quite differently than predicted by the standard VDMOS model. For the 20mA to 600mA range, Id behaved more like (Vgs-Vth)^3.3. I stumbled onto the EKV model and was able to make that work, but yesterday I discovered this thread and the new LTSpice version with Ksubthres added to the VDMOS model. I think it will solve many simulation issues I have been wrestling with. Many thanks to Mike Engelhart.