I am very interested in feedback on this design (which is based on patents held by http://www.passlabs.com and thus not available for anything but research). To scale power, simply change rail voltages (and increase value of feedback resistor to get enough front-end voltage gain to drive outputs to saturation). To change level of Class A drive, increase bias resistors. To improve "supersymmetry" and reduce gain, increase value of resistor between bottom of input FET's.
The 1M resistors are there for simulation purposes and would ordinarily be smaller. And yes, I simulated this design using a Spice CAD package.
We are probably looking at something very close to a commercial X-series amp (without embellishment). If you like feedback, place the feedback loop around the output transistors.
[Edited by Petter on 02-21-2001 at 07:52 AM]
Can't see it.
yeah the image doesnt come out.
can you send it be email maybe.
Sorry, but can't see it - Send it per email - thanks.
Please send me the GIF on my email
Tried MSN too, but still the gif won't come up. I have a MSN account to log on. The page comes up blank.
I'd like to see this. Email it to me.
OK, I saw it this time. It's interesting. So, the PSPICE software told you this would work?? Are you going to attempt it Petter, or are there things that need to be worked out yet?
I too had problems seeing the picture. I signed in using my ordinary hotmail-account but still got up a blank page. When I joined the community (note: "Stax OTL DC coupled amp design (fun with fibrillation)", created a new member) it all started working, et voilą, there it was.
Petter: I'll look at it later, but I guess there are people on this forum that can give you more intelligent input than I can since I'm not an EE.
[Edited by Matti on 02-21-2001 at 02:48 AM]
Got the image up, and some answers
Finally managed to get the image to show (i.e got the file hosted on this server).
I simulated using Circuitmaker which is a great piece of software -- so easy to use (and they do have a demo version available at http://www.microcode.com). The frequency response, I eyeballed to 30KHz or so -- it would be higher with fewer output transistors (number of output devices is somewhat arbitrarily chosen -- that is I did some quick calculations but no deep analysis, and to allow for future expansion if I need more power), or feedback placed at speaker terminals. A particularly cool feature about this design is that it scales so well -- hardly any changes other than PSU voltages are required for different power output level. Also note that output transistors need only be mathed in quad's when you cut to the bone.
The key to this design is accuracy of current sources. I strongly believe they should be FET type sources since any gate current will mess up the balance between halves. I am probably being a bit paranoid about this "base current" and the accuracy of current sources, but I really don't want an amp that is going to need adjustment other than for quiescent curren in output stage. I have two basic designs ready for this, one relying on significant voltage drop (degradation), the other on active device physical parameters. Op-amp based versions would work, but I don't like them very much.
What is missing is ajustment for quiescent current (now shown as fixed resistors), gate protection for transistors (zeners) and schematics for current sources. Note that the design requires balanced input signal like the original. It is very easy to make an unbalanced to balanced input stage and improve performance (frequency response etc.). What is also missing is compensation to control phase margin at very high frequencies.
I am indeed planning to build this design, but will tinker with voltage levels, number of transistors and resistor values, particularly the one between input transistors, as well as feedback resistors (gain selection). As I will be needing a single-ended to balanced front-end anyway, I will probably change these values to reflect the gain I can get out of this input stage as well.
As a concequence, I am very interested in feedback whch you can post here or send to me by mail.
As a non-EE who briefly thought of doing something very similar, but soon realised it was beyond me, I'm very impressed!
Have you tried the values for the 'virtual ground' resistors cited in the patent, and was there a particular reason for using 1M/5k for the purposes of the simulation?
Don't know whether NP will be giving his usual support to this one!
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