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-   -   Simplicity and elegance, feedback wanted! (https://www.diyaudio.com/forums/solid-state/365685-simplicity-elegance-feedback.html)

SSassen 6th January 2021 08:44 PM

Simplicity and elegance, feedback wanted!
 
5 Attachment(s)
Hello gents (ladies?), I was hoping to get a bit of feedback on the amplifier design I've been working on, as in an amplifier design you can't have too much feedback, right? But before I arrive at what sort of feedback I'm looking for exactly please allow me to provide some background about the design.

As I was looking to busy myself during lockdown I revisited some of my earlier designs, some dating back well over a decade. This particular design initially started out as a rather elaborate exercise with lots and lots of transistors utilized to build cascodes and a plethora of precision current sources and mirrors. Then I realized that there's beauty in simplicity and elegance, so I started reducing it to something a bit more rudementary, which led me to where I'm currently at.

Upon looking at the schematic anyone that has ever dabbled with amplifier design will see the familiar three stage approach, but with optimizations left and right, let me briefly go over them to illustrate why I arrived at them:

1) The classic LTP input stage has a Wilson current mirror and features a pickoff point for the ETMC (Edmond Stuart) compensation I'm using (C12 and R37). The Wilson current mirror provided noticeable benefits over the standard current mirror, for the cost of an extra two transistors, so I figured that was worth it.

2) The current source feeding the input pair is the regular two transistor variety, nothing fancy here, I tried elaborate schemes, but those didn't seem to provide any benefit, but willing to try again if needed.

3) The VAS, to be honest I prefer to use the more correct term TIS, is your typical contraption, Q19 and R38+R39 as well as C12 and R37 provide the ETMC compensation. Q7 is the typical EF transistor with R40 used to protect Q7 during clip. Q17 serves a similar purposes but during a shortciruit at the output. Q18 makes sure the TIS can adequately drive the output stage. The TMC compensation rounds off the TIS stage and hooks directly to the output stage.

4) The output stage itself uses two pairs of Exicon lateral MOSFETs as that saves me a lot of headaches, and transistors, coming up with a foolproof protection if I had used a BJT output stage. They're biased a little beyond the point where their tempco becomes positive, which means they'll automagically provide temperature compensation. Due to the absence of a 2nd breakdown and the fact that lateral MOSFET's aren't a dead short when driven hard they have a wide SOA and I could get away with a simple protection mechanism.

Transistors Q15+Q16 and diodes D3+D4 take care of that, as they will reduce the drive voltage and limit the maximum current to about 8A per lateral MOSFET, which yields about 15A peak, more than enough for most loudspeakers.

So, and this should really have been in the first paragraph, what are the requirements I set for the design of this amplifier? Well, a balanced input paired with simplicity and elegance is one, getting as close to the proverbial holy grail of -120dB/100W/8R/20kHz is another. With the current design the simulator optimistically reports 0.0003%, or rather -110dB, so quite close to target.

Closed loop gain shows ~88 degrees at the 0dB point, and the gain plot looks nice and smooth, as does the phase plot. That, in a nutshell, sums up the design. What I would love your input on is whether there's any elegant ways to further improve performance I might have missed?

Please find the relevant plots attached, as well as the LTspice .asc file for the amplifier design.

Thanks for applying feedback! I'm looking forward to applying your ideas and hopefully further improve on the design!

AKSA 7th January 2021 12:25 AM

Very nice amp, Sander.

Do you think that the two drivers are needed, given that gates of laterals are not very hungry?

Including a Vbe bias generator is unusual. How does the quiescent vary through the operating temperatures?

Elegant compensation, excellent current limiting, and high loop gain. Very low distortion, and nice profile.

Cheers,

Hugh

suzyj 7th January 2021 01:23 AM

Looks cool, but is Q16 a bias compensator? Laterals have negative temp coefficient, as you mentioned, so no need for that.

SSassen 7th January 2021 07:07 AM

Quote:

Originally Posted by AKSA (https://www.diyaudio.com/forums/solid-state/365685-simplicity-elegance-feedback-post6478665.html#post6478665)
Very nice amp, Sander.

Do you think that the two drivers are needed, given that gates of laterals are not very hungry?

Including a Vbe bias generator is unusual. How does the quiescent vary through the operating temperatures?

Elegant compensation, excellent current limiting, and high loop gain. Very low distortion, and nice profile.

Cheers,

Hugh

Thanks Hugh!

The drivers reduce the THD by about 10dB, so their addition was well worth it in my opinion. They’re biased at 16mA to better be able to suck the (significant) gate charge out of the MOSFEts.

The bias generator is there to better control the temperature drift if you bias the lateral MOSFETs below the point where their tempco switches from positive to negative. In that case there’s significant drift in the heatsink temperature, the simple Vbe bias generator keeps that in check. The prototype will need to show whether this is a real world requirement, if not I’ll revert back to a simple trimpot.

SSassen 7th January 2021 07:09 AM

Thanks Suzy!

Hugh suggested the same, please see my reply to him for an explanation why.

Quote:

Originally Posted by suzyj (https://www.diyaudio.com/forums/solid-state/365685-simplicity-elegance-feedback-post6478717.html#post6478717)
Looks cool, but is Q16 a bias compensator? Laterals have negative temp coefficient, as you mentioned, so no need for that.


AKSA 7th January 2021 08:21 AM

Sander,

Thanks for the answers....... helpful and instructive.
Of that 10dB reduction of THD was this 2-5 harmonics, or 5-20 harmonics? I ask because the Zout of the emitter followers is typically 26/12= 2R yet the stoppers are 47R and it seems to me that the impedance issue is secondary; it could be caused by the fast flow of charge into and out of the gate, and this could be achieved with highish current (18mA or so) between two collectors.

How did you arrive at the 47R stopper values? I have never seen definitive values given for the ECW lateral series..

I'm very much impressed with the THD, very low indeed.

Hugh

BesPav 7th January 2021 08:45 AM

Hi, Sander!

If you replace Q6 to the KSC3503/KSA1381 pair wired as diodes you'll pick near ideal thermal tracking of the driver stage.

By the way, you can pick much more feedback depth and a way higher unity-gain freq with such an output stage.

Ultima Thule 7th January 2021 08:52 AM

You want feedback, I like your new 6C33 avatar, they look like small Androids! :)

Ok, I have more like questions than any real feedback as I am maybe not 100 about all the fascinating intricate circuits in this amplifier.

First I am curious how the so called compensation network is supposed to work circulating around C12 R37, to my eyes it looks like it's adding positive feedback gain at higher frequencies, how or what exactly is it doing?

R40 on Q7 collector, isn't it possible to omit this resistor as it will degrade the BW and increase distortion through the non-linear miller C, if we want to protect Q7 from saturating and burning up, then perhaps a low Vf diode with anode to its base connected to Q8 collector would ensure that wont happen as when Q8 saturates it will pull Q7 base down.

Next, I am wondering if Q18 really is necessary as the lateral Op FET's have so low Crss and are already buffered with Q9 and Q10. A suggest modification could be to change Q8 for a smaller signal bjt and cascode it with ksa1381, although this isn't that necessary as Q8 is already buffered by Q7.

The current limit through output FET's set to 15A seems not the correct figure, maybe I am wrong but it looks rather like the double or even quadruple, that is because when one side of the OP stage is conducting, the other side is turned off, therefore there will be a voltage fall only over R24/25 or R26/27.
So if one assume there's roughly 0,7V per silicone device (1N4148 is actually lower, maybe closer to 0,5), in order for the Q15 and Q16 to activate we would need 0,7+0,7+0,5+0,5=2,4V, and 2,4V over each resistor pair (only the upper or lower pair) would yild 24A per R, or for a double 48A peak.

Oh, and a last one, some thoughts on Q6 Vbe multiplier, it may be too aggressive and pull back quiescent current too much, the laterals tempco goes neutral at around 100mA and negative above that, so what could be one viable option if we want to keep the Vbe multiplier is to leave Q6 stay put on the PCB instead of attached to the heat sink directly, that would make it react much gentler and only sensing the total ambient temperature adjusting less aggressively.
Although a simple R trimpot is actually enough with latfets.

Cheers Michael

bucks bunny 7th January 2021 09:08 AM

5 Attachment(s)
Some yrs ago I got my hands on some original NOS 2SK135/2SJ50. This inpired me, after decades, to design an latFET-amp using extensively LTSpice. Out came a Monoblock with one pair of LatFETs intended as ultra-rigid lab ref amp with a bandwidth of several 100kHz. The technical data measured at the prototype are excellent and should be quite encouraging to build your own latFET amp.

SSassen 7th January 2021 11:08 AM

Quote:

Originally Posted by AKSA (https://www.diyaudio.com/forums/solid-state/365685-simplicity-elegance-feedback-post6478949.html#post6478949)
Of that 10dB reduction of THD was this 2-5 harmonics, or 5-20 harmonics? I ask because the Zout of the emitter followers is typically 26/12= 2R yet the stoppers are 47R and it seems to me that the impedance issue is secondary; it could be caused by the fast flow of charge into and out of the gate, and this could be achieved with highish current (18mA or so) between two collectors.

I see this reduction at 100W/8R/20kHz, I've not been looking at lower frequencies to be honest as my thinking was that those automatically will be significantly reduced as the loopgain is much higher at lower frequencies.

Quote:

Originally Posted by AKSA (https://www.diyaudio.com/forums/solid-state/365685-simplicity-elegance-feedback-post6478949.html#post6478949)
How did you arrive at the 47R stopper values? I have never seen definitive values given for the ECW lateral series.

These seem to work well with the optimized VDMOS (with treshold) models I used for the ECW series in the simulator. I'm going to take the pragmatic approach to optimizing them IRL though, simply by swapping out values and running successive THD measurements on the prototype. Bob Cordell used a different approach with RC networks on the gates, might give that a try too.

My thinking is that I can spend weeks in the simulator and never get a definitive answer whilst an afternoon spent on the workbench with a prototype will give me better results quicker.

Quote:

Originally Posted by AKSA (https://www.diyaudio.com/forums/solid-state/365685-simplicity-elegance-feedback-post6478949.html#post6478949)
I'm very much impressed with the THD, very low indeed.

Cheers, this was a careful balancing act with a lot of Monte Carlo scripting in LTspice to allow me to zero in on optimal component values. Luckily I don't have 40+ transistors in this design so this was somewhat manageable still.


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