SRC4392 problem with DIR / SPDIF
I’m usi SRC4392 as follows:
SPDIF input (96kHz, 400mV p-p) —> RX2 DIR (MCLK) —> PORTA (as master, MCLK, 96 kHz)
When check with oscilloscope
- SPDIF signal ok
- MCLK ok, 24.576 MHz
- LRCLK ok, 96 kHz
- BCK ok, 6.144 MHz
- SDOUTA - no signal
I have also checked /LOCK pin and it is high - DIR unlocked.
Any idea what can be wrong?
Registers are configured as follow:
- 01 3F - power all on
- 7F 00 - page 00
- 03 29 - DIR to PORTA, 24b I2S, master
- 04 01 - MCLK, /256
- 0D 09 - RX2 input, MCLK
- 0F 22 - 24.576 MHz
- 10 00
- 11 00
When read registers they are configured properly (besides 01 which is triggering reset when I read it)
I have also programmed interrupts (unmasked, level) for audio signal and DIR lock:
- 16 24
- 18 20
- 19 08
And when I read reg 14 I’m getting 04 - DIR not locked.
Any idea what to do differently? It seems that receiver DIR is not getting inout SPDIF signal to PORTA...
Shouldn't 04 01 be 04 08? Presumably the master clock is not synchronous with the SPDIF data stream.
For what it's worth, I use these values to get an DIX4192 to send its SPDIF data to port A, and a DIX4192 is supposed to be firmware compatible with the SRC4392 as long as you only use the serial ports and S/PDIF interfaces:
// All address and data values hexadecimal!
// Address 01, value 32: DIR on, DIT off, port B off, port A on,
// general enable on, reset off.
// address 03, value 29: port A in master mode, signal from DIR, audio not muted, 24 bits I2S
// address 04, value 08: RXCKO divided by 128 as LRCKA
// address 0D, value 08: RXCLK to MCLK, input 0 to DIR
// address 0E, value 1D: sound muted when the DIR is not locked, clock from
// PLL2 divided by 4 (assumes 44.1 kHz sample rate, I update it later),
// RXCKO output on, PLL2 free-running when out of lock
// addresses 0F...11, values 21CB02: PLL1 set to P = 2, J = 7, D = 2818, as
// recommended with a 27 MHz reference clock
Thanks Marcel - I believe reg 04 is to configure clock source for PORTA when running as master. This clock source can be either MCLK, RXCKI or RXCKO. I'm using MCLK as a clock for all blocks (DIR and PORTA).
ACLK[1:0] Port A Master Clock Source
These bits are used to set the master clock source for Port A when configured for Master mode
ACLK1 ACLK0 Master Clock Source
0 0 MCLK (Default)
0 1 RXCKI
1 0 RXCKO
1 1 Reserved
Do you think the clock for PORTA should be RXCKO? (is RXCKO internally routed between DIR output and PORTA input?)
Its been awhile since I programmed SRC4392, but we can probably figure it out together.
IIRC, an incoming SPDIF stream was clocked by the source sending it out. Therefore the DIR must be synced to the VCO clock derived from the SPDIF receiver. The incoming audio then gets routed to the SRC to get resampled in time with the MCLK (or RXCKI) crystal clock. The SRC output frequency is set is set to some divided MCLK value. (There are two clock input pins to allow resampling to either 44k or 48k family output sample rates, and or for other possible design scenarios) The SRC output gets routed to a PCM serial port.
Also, IIRC, the only way to avoid having to resample incoming SPDIF might be if the SPDIF source was synced to the SRC4392 SPDIF output (or otherwise somehow synced to MCLK).
On second thought, it looks like Marcel's solution works too. Its just that if everything is clocked from the receiver VCO clock, jitter is likely to be worse than if resampling to local low-jitter crystal clock.
Thanks a lot Mark. Originally I used DIR —> SRC —> PORTA but sometimes it worked but sometimes not. So I decided to go step by step and route DIR —> PORTA first. Using SPDIF signal with 96 kHz LRCLK as well as setting up PORTA with MCLK 24.576 MHz divided by 256.
My understanding is that DIR can be used with external MCLK 24.576 MHz (specified by registers 0F, 10, 11) while internal PLL is able to lock to wide range of frequencies like 44.1, 48, ... 96 kHz.
Do you think that there is anything wring with this configuration?
As a result of problems more or less like that, everything either needs to run sync'ed to one master clock, or else SRC has to be used to resample data to work with the receiver crystal clock. Of course, it could be as Marcel suggested, just use the SPDIF receiver PLL-based clock as the one master clock source for everything, but then the Port A output will probably more jittery than if a crystal clock were used along with resampling. You have to choose your poison, so to speak. Suffer the consequences of resampling or suffer more jittery PCM output.
If you tried using SRC before and it only worked sometimes, could be there is some other problem? Did you try troubleshooting with a scope and or look at the SRC SPDIF status registers for possible clues?
Also, I might mention that besides using a low-jitter clock for SRC, it can help some more to put the clock on its own dedicated LDO regulator attached to the SRC4392 ground plane and located close to the clock module. Same type of thing we do with dacs to help minimize jitter. In addition, SRC4392 is an excellent SRC (as hardware SRCs go) so probably no worries about hurting sound quality by resampling. When resampling for whatever reason, it usually seems to sound best to upsample as much as reasonably possible. Say, perhaps to 192kHz. Might we worth a try to see if you think it sounds better.
There is something funny about the DIX4192/SRC4392 S/PDIF receiver when you want to use it over a large range of sample rates and want to use the clock it recovers as the clock for one of its I2S interfaces. You have to read out a parameter RXCKR which indicates the ratio between the output frequency of PLL2 of the DIX4192 and the sample rate, and then update RXCKOD accordingly. This sets the division ratio of the post divider of PLL2. I use the following Verilog code (plus code that actually reads RXCKR and writes RXCKOD via SPI) to always get a clock at 128 times the sample rate, like the I2S interface requires when ADIV1 = ADIV0 = 0:
always @ *
2'b00: rxckod = 2'b00;
2'b01: rxckod = 2'b00;
2'b10: rxckod = 2'b01;
2'b11: rxckod = 2'b10;
Well, I can go back the original setup DIR —> SRC —> PORTA but also in this case there is no output signal at PORTA output (it somehow worked before with the same req setup, but not stable and not working right now). What I used in this case as setup is:
- DIR using MCLK, PLL setup for 24.576 MHZ (reg 0F, 10, 11) - input SPDIF signal 44.1 kHz or 96 kHz (tried both), routed to SRC
- SRC using MCLK, output LRCLK freq 96 kHz routed to PORTA
- PORTA using MCLK 24.576 MHz, div 256, master, 96 kHz
Is there anything wrong with this setup? I thought it should be ok to use MCLK as source clock for DIR, SRC and PORTA. Or not?
Thanks Marcel. So if I go with SPDIF —> DIR —> SRC —> PORTA I2S setup while having SPDIF input freq 44.1 kHz - 192 kHz and SRC / PORTA output freq fix 96 kHz what is the right clock routing for DIR, SRC and PORTA? (I do have an on board 24.576 MHz oscillator on board which I used for all three DIR, SRC and PORTA now, PORTA as master using MCLK)
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