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krfkeith 1st June 2013 08:37 PM

Ultimate Open Source XMOS USB-I2S: The source to end all sources.
There are a host of options on DIYaudio for I2S, but none of them seem to completely fit the bill, and most importantly, very few are open source! Therefore, I propose a group project to build the ultimate USB-I2S.

In terms of audio, it should have the following features:
16-bit, 24-bit, 32-bit
44.1Khz 48Khz 88.2Khz 96Khz 176.4Khz 192Khz 352.8Khz 384Khz
also, DSD64 and DSD128

I propose, as the chip, an XMOS.

Now the questions:
  • Asychronous or Sychronous? Which is better?
  • What about reclocking and/or FIFOs? I've heard about so-called "generic" FIFO chips from Cypress. What about the Potato Semiconductor mod for the Almanero?
  • Which isolators?
  • DSD can be run to the XMOS via DSD over PCM, but how is this converted to DSD output for the DAC?
  • What clocks? How many? Does there need to be a separate clock for each sampling rate?
  • I've heard about a clock from silicon labs where the frequency can be programmed, can that be used?
  • Is there anything else I'm missing?

I have to say, all of this is very overwhelming! There are just so many options!


blueskull 13th June 2013 11:35 AM

1. Async or Sync, if you have an ASRC, you won't care about the original jitter. Even if the PC give out a wrong frequency, i.e. 1000ppm higher, it won't affect you. You definitely can't tell 1kHz or 1.001kHz.
2. Reclocking is better preferred. Reclocking can reduce jitter and eliminate the need of sync USB, and it can guarantee the DAC operates at a much more higher sample rate than 20kHz. It's a common misunderstood that SRCs will improve details by interpolation, however, if you really did wrote an ASRC or SRC, you will know there is a digital LPF in it, so it can't really improve details. However, SRCs can elevate DAC's working frequency, that can effectively isolate conversion noise to audible frequency, thus simplifies the circuitry of analog LPF. Furthermore, an ASRC without input buffer will NOT reduce jitter, due to even if the jitter to DAC is reduced, the jitter to the SRC's decimation filter is NOT reduced, therefore it still degrades the SNR and DR. However, an ASRC with a buffer and a DPLL or a PLL, can actually mitigate the jitter issue. Independent ASRCs such as AD1896 will be prefered, while integrated ASRCs inside ADSP-21XX series was preferred as well. They can achieve 140dB DR, as AD1896 can. My currently approaching is not XMOS, but an Altera FPGA. XMOS products with ASRC seems not performing well. My Bladelius DAC performs with RMAA worse than my Asus Essence STX.
3. Isloators: If you are mentioning an isolator to isolate IIS or LJ or RJ or data that bypasses DAC's internal filters, I will recommend TI's ISO series, because they use 2 isolators, one for low freq and DC, while the other one for high freq, which is not modulated, which mean you can get high frequency signal pass the isolator without clocked by the isolator's internal PWM clock, that will result in a better phase matching.
4. DSD? If you don't want to get troubled in patent issues and you don't want to connect to a DSD system, don't use it. DSD is for external connection, just as AES/EBU, it is not intended to be used as an internal connection.
5. Clocks. As soon as you have a precise PLL or DDS with an ASRC, why bother on multiple clocks? Clocks could be generated by external PLL or DDS. Even generated by DDS, buffer it with a PLL is preferred, to get lower phase noise. After the PLL buffer, a digital logic buffer is preferred to distribute the clock into DACs and FPGAs. Do NOT EVER use the FPGA's internal PLL and IO as clock generator and buffer, that is very jittery, unless you use a PLL intended for SERDES, which shows in Vertex or Stratix or Lynx or Arria series of FPGAs, which are far too expensive for audio use.
6. Those programmable clocks are intended to generate high frequency clocks and they uses PLL as clock multiplier, they are designed and optimized for telecommunication, not audio. And, they are hard to obtain from distributors, and not quite easy to get sampled. Generally, a NON TCXO will perform well if a PLL buffer is used in the very backend of clock signal chain.
7. If you want to construct a 140dB ASRC, be sure to use FPGAs, because DSPs are designed to do tens of taps of FIR calculation, not hundreds. With a 0.4 roll-off raising cosine FIR filter, you need 500 taps to obtain 140dB DR at 100ksps, Fcut=30kHz. FPGAs can do actually any sort of calculation with highly optimized performance, of course, a little bit more expensive, but cheaper than high-end DSPs, and consumes lower power.
BTW, don't drive a DAC to its upper limit of sample rate, that may deteriorate its THD and IMD performance. I'm currently designing an external DF and THD reduction digital system, as well as a linear interpolation analog system, see if it's possible to transcend the performance of ES9018, using only cheap and massively available PCM1792A.
Currently I've no much time on it, because I'm facing my semester exam, and follows GRE and TOEFL test. I'll continue my super DAC project on approx. October 15th. If anybody have any suggection, pls PM me.

GTrenchev 13th June 2013 10:44 PM

I want I2S input for ADC :)

s3tup 14th June 2013 02:31 PM


Copying this design would be a great starting point, as it has the right flavors in right places.

luxury54 14th June 2013 04:54 PM

there is a new design of xmos async interfcae on ebay, it is coming also boxed with I2S tap points inside the box

Commpleted 192K 24bit Xmos USB to Fiber Coaxial Output I2S Asynchronous WLX | eBay

item No. 151061728734

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