Synchronizing SG3525

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I want to synchronize my SMPS controller to a fixed clock derived from my Class-D amplifiers (divided by 2) to avoid any potential noises produced by beating between all them.

My amplifiers run at 300KHz, and after a comparator, counter and optocoupler I get a clean TTL 150KHz waveform, because I want a SMPS switching frequency of 75KHz.

I want to feed it (with a small cap in series) to the SYNC input of the SG3525 controller.

My questions are:

a) Can the Rt, Ct and Rd components in the SG3525 be set so the approx. free-running switching frequency is also 75KHz, or do they need to be set at a much smaller freq. so SYNC operates correctly? (I would like the control board to be operative with or without synchronization, at approx the same sw. frequency)

b) Must this sync signal be 50% duty cycle or can it be, say, 25%?

Best regards,
Pierre
 
The internal oscillator of the SG3525A has to be set up to work at a slightly lower frequency than the (divided) one coming from the class D amplifier, and a narrow pulse has to be applied to the SYNC input in order to terminate prematurely SG3525A cycles to match class D cycles. The pulse has to be long enough to allow the SG3525A to react, but still very narrow because the oscillator will be frozen until SYNC input becomes low. You may try using some logic gates (probably involving flip-flops) to apply the SYNC pulse until the CLOCK output reacts, then it should be no longer needed.

The best thing that you can do now is to build an experimental version into a breadboard and investigate real IC behaviour. I learnt a lot about SG3525A and other control ICs that way (and I mean details not told in the datasheet).
 
Synch'ing the SG3525

Pierre,

The only Application Note I could find is one from Silicon General, PS-7, "Synchronizing the SG1525A PWM". Section 1 of this sheet (Synchronizing One Device to an External Clock) is as follows:

[A. Program the SG1525A oscillator with R(t) and C(t) to free-run at a frequency 10% slower than the external clock frequency.

B Drive the SG1525A SYNC pin terminal (pin 3) with the external clock. Input impedance is 2kW. The clock amplitude should be greater than 2 volts and less than 5 volts. Pulse width should be at least 300nS for reliable triggering, but should not exceed the free-running oscillator clock pulse width by more than 200nS.]

Since you want to synch the '3525 at 150kHz, these times should not present a problem. If you were synch'ing it at the 300kHz, you might run into some problems, as the '3525 oscillator's max. frequency is ~400kHz.

EVA is right that there are some things that can't be learned from datasheets alone. I've looked everywhere for anything I can find on synch'ing the SG3525, MC33025, TL494, UC1846, and other popular PWM chips, and this Application Sheet is the best thing, by far, I have seen for the SG3525. I have worked on an "Application Note" of my own to consolidate the synch schemes for all of these chips so I can see them all at-a-glance. If I get some time, I will scan it and post it.

I got this sheet some time ago (before the www), so I have not gone to SG's website to see if it has made it into cyberspace yet.

Hope this helps,

Steve
 
I have tested with a programmable function generator, and a TTL 150KHz signal synchronizes the SG3525 perfectly, with duty cycles from 10% up to 50% (so it seems that not so narrow pulses are needed).
The signal generator signal goes to the base of a so2222 NPN, the signal is taken from the collector (with 1K pullup to Vref=5.1V), and passed to SG3525 SYNC pin through a 100pF capacitor.

The chip's free running switching frequency is set to 70KHz. As soon as I connect the generator, it changes to 75KHz. If I reduce the generator frequency to less than around 144KHz, it de-synchronizes, as expected (free running oscillator must be set a little below desired sync frequency).

All this tests have been done with the SG3525 in open loop (max. duty cycle, around 90%), should I expect it to be ok when it really makes PWM when the SMPS loop is closed?
 
Sorry, not yet. My optocoupler has failed due to a stupid shorcircuit while measuring, so I won't be able to do more measurements till tomorrow. I will check that.
It may be that the 100pf series capacitor is acting as a high-pass filter for the sync pulses, allowing only a narrow peak independently of the input duty-cycle. But I will check and come here with the conclusions...

Thanks for your help
 
Pierre,

Eva is right... excessive pulse width will suppress the sawtooth... depending on your application (overall switching duty-cycle) some of this is allowable.

It is possible to use a simple cap in series (differentiator) to effect a narrower pulse. You just have to experiment a bit. Be sure to use a resistor in parallel with input of the chip so that chip to chip and temperature variations do not detune your differentiator.

;)
 
I have measured the SYNC signal entering the SG3525, in fact there are peaks of 5V amplitude and around 1.5us width (exponentially decaying), so the 100pF capacitor is derivating the input pulses, as you predicted.
The negative portion of the pulses is clamped by a 1n4148 to GND, in order to avoid negative peaks at SYNC input.
 
The motivation of this synchronisation circuit was to avoid a slight but definitely noticeable tone (with variable frequency) that appears when I connect my PSU to my (clock based) Class-D amplifiers.

I think that this is due to beating between the SMPS and the amp. clock, due to the small residual peaks that the supply lines have at the supply's switching frequency.

The output of my suppy has 47uH coils followed by 2x3300uF per rail. Is there something I can do to improve the situation (adding a choke, etc) before synchronizing all? I tried adding a 10uH choke in series with each rail at the amplifier (it has onboard 220uF capacitors so it should form a LC filter) with no audible difference.

Best regards,
Pierre
 
any ideas to clean up the supply and avoid the necessity of synchronization?

I've wondered this myself, Pierre- this is a great question. I've seen several amplifier manufacturers such as Crown use a master clock for SMPS and class-D amplifier. QSC Audio derives a more accurate clock to drive the SG3525 in thier amps supposedly to prevent beat frequencies from several of the same amplifier used at the same time. All thier amps are tuned to the same frequency supply. Also, I think SMPS in TV's are sometimes syncronized to the scan rate to reduce picture interference.

I'm wondering if this is the "easy way out" or actually a necessity as well.

Also, what about self oscillating class-D or variable frequency SMPS? Is there some way to synchronize these, or is it not necessary?

Good discussion!
 
Hi, I have been working on variable frequency SMPS designs. The variable frequency is the by-product of zero voltage switching circuitry advancing or retarding the timing of the control signals to transformer drive transistors like MOSFETs. The goal is to have a circuit which limits high frequency harmonics in the higher power portions of the circuit to the low single MHZ or even hundreds of KHZ range. Hopefully the relatively low frequency harmonics in the circuit will be easy to contain locally and not be radiated or conducted outside the circuit without using bulky filters. I experimented on a flyback circuit powered by 12v which produced little harmonic content above about 100KHZ.

I have been looking for a sort of magic formula of SMPS design. However, I have been finding that trade-offs become necessary in all the ideas I have tried.
 
Yesterday while measuring my sync. circuit and gate signals in my SMPS, I found that, although the SG3525 is synchronized with my amps (no beating nor noise), there are strange pulses as if synchronization wasn't done correctly.
As a reminder, I take the output of my 6N137 (with a pull-up to 5V1) directly to the base of a 2222 BJT with a 1k from collector to 12V (emitter to GND). I take the collector signal and couple it to the SYNC pin of the chip through a 100pF cap, with a 1n4148 from SYNC to GND in order to clamp the negative peaks.
I have inspired in a similar schematic in this forum, he also used 6n137 optocoupler, but he also has a 100pF in parallel from SYNC to GND.

Is this cap necessary, perhaps to remove noise and clean up the sync signal, so perhaps I have these problems because I haven't included it? (yes, I know, I must experiment, but I won't be able until tomorrow ;-)
 
Hi All,
I want to sync two SG3525, clocked at 75Khz with a separate oscillator running at 85Khz. I plan on using two opto couplers connected to the sync pin of the 3525 with a resistor between the sync pin and +Vcc. Will this work reliably or do i need to use a buffer between the opto and the sync pin. Any info shared on this topic will be appreciated.
 
Hi, Q S C use this system. Look the green circle in the photo P L 3 8 0 amp service manual. Take in count that are using GDT in the SMPS. If is not too late for this
 

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