VR1/R1=CCSmAI had to reduce the R1 negative tup to 2.7R. So that the voltage does not decrease when the load is connected
One thing is there is some Vbe voltage loss in the start for Q2 due to transistor temperature coefficient physics. Because you use SMD probably more pronounced. That steals some current from the Vref and decreases Vout until thermally settled. Another thing is you need to allow enough spare current beyond load, say 100mA more. With R1=3.9R you had 230mA limit (0.9V/3.9R) and 170mA load (17V/100R).
So I did everything right? 170mA+100mA=270mA>230mA (3.9R)
That's +60mA spare, it better was more. I don't know about Q1 Vbe ~0.9V, seems bit high or maybe right, the standard reg uses through hole BC327/337.
How much rectified DC you got on the input?
Now you have the usually expected voltage range on R1. By the way your transformers show relatively high regulation % loss under load. And/or its your bridge diodes loss. How much Vf drop on each diode?
Neg R1-0.93V Pos R1-0.91V
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