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Power limitations for LLC-smps for amplifier
Power limitations for LLC-smps for amplifier
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Old 25th November 2017, 02:36 PM   #11
MorbidFractal is offline MorbidFractal
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OK... So I mess about with my LTSpice model.

Code:
Version 4
SHEET 1 1176 1080
WIRE -64 32 -416 32
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WIRE 944 912 656 912
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FLAG -416 432 0
FLAG 976 32 VOUT
IOPIN 976 32 Out
FLAG -192 112 DRVA
IOPIN -192 112 In
FLAG -192 288 DRVB
IOPIN -192 288 In
FLAG 976 528 VOUT
IOPIN 976 528 In
FLAG 448 768 VERR
IOPIN 448 768 Out
FLAG 944 944 0
FLAG -48 544 0
FLAG -48 688 0
FLAG -336 544 DRVA
IOPIN -336 544 Out
FLAG -336 656 DRVB
IOPIN -336 656 Out
FLAG -256 592 0
FLAG -256 704 0
FLAG 176 560 PMOD
IOPIN 176 560 Out
FLAG 176 592 DMOD
IOPIN 176 592 Out
FLAG -336 784 B
IOPIN -336 784 Out
FLAG -336 752 A
IOPIN -336 752 Out
SYMBOL ind2 368 128 R0
WINDOW 0 -64 44 Left 2
WINDOW 3 -65 70 Left 2
SYMATTR InstName LP
SYMATTR Value 340µ
SYMATTR Type ind
SYMBOL ind 256 48 R270
WINDOW 0 59 60 VTop 2
WINDOW 3 62 59 VBottom 2
SYMATTR InstName LLeak
SYMATTR Value 62µ
SYMBOL cap 368 256 R0
WINDOW 0 -65 12 Left 2
WINDOW 3 -66 37 Left 2
SYMATTR InstName CRes
SYMATTR Value 62n
SYMBOL ind2 480 240 R180
WINDOW 0 -45 68 Left 2
WINDOW 3 -56 43 Left 2
SYMATTR InstName LS
SYMATTR Value 32µ
SYMATTR Type ind
SYMBOL diode 544 48 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName DR1
SYMATTR Value DID
SYMBOL diode 608 96 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName DR2
SYMATTR Value DID
SYMBOL diode 608 240 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName DR3
SYMATTR Value DID
SYMBOL diode 544 352 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName DR4
SYMATTR Value DID
SYMBOL cap 800 256 R0
WINDOW 0 38 20 Left 2
WINDOW 3 38 49 Left 2
SYMATTR InstName CFA
SYMATTR Value 1000µ
SYMBOL sw -64 192 M180
WINDOW 0 -78 122 Left 2
WINDOW 3 -77 97 Left 2
SYMATTR InstName S1
SYMATTR Value MSW
SYMBOL sw -64 368 M180
WINDOW 0 -75 129 Left 2
WINDOW 3 -75 103 Left 2
SYMATTR InstName S2
SYMATTR Value MSW
SYMBOL diode 32 160 R180
WINDOW 0 -57 43 Left 2
WINDOW 3 -49 21 Left 2
SYMATTR InstName DB1
SYMATTR Value DID
SYMBOL diode 32 336 R180
WINDOW 0 -57 46 Left 2
WINDOW 3 -50 22 Left 2
SYMATTR InstName DB2
SYMATTR Value DID
SYMBOL cap 96 96 R0
WINDOW 0 39 19 Left 2
WINDOW 3 40 45 Left 2
SYMATTR InstName CP1
SYMATTR Value 470p
SYMBOL cap 96 272 R0
WINDOW 0 36 18 Left 2
WINDOW 3 38 43 Left 2
SYMATTR InstName CP2
SYMATTR Value 470p
SYMBOL voltage -416 176 R0
WINDOW 0 36 43 Left 2
WINDOW 3 38 69 Left 2
SYMATTR InstName VBUS
SYMATTR Value 395V
SYMBOL Opamps\\opamp 592 656 M0
WINDOW 0 9 95 Left 2
SYMATTR InstName U1
SYMBOL voltage 816 640 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 -32 56 VBottom 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName VRef
SYMATTR Value -6
SYMBOL res 816 512 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 100K
SYMBOL res 640 512 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value 10K
SYMBOL res 704 656 R270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R4
SYMATTR Value 10K
SYMBOL SpecialFunctions\\modulate 352 528 M0
SYMATTR InstName A1
SYMATTR SpiceLine Mark=160K Space=220K
SYMBOL Digital\\dflop -48 544 M0
WINDOW 0 48 -19 Left 2
SYMATTR InstName A2
SYMATTR SpiceLine Vhigh=15V Vlow=0V
SYMBOL Digital\\and -272 496 M0
SYMATTR InstName A5
SYMATTR SpiceLine Vhigh=15V Vlow=0V
SYMBOL Digital\\and -272 608 M0
SYMATTR InstName A6
SYMATTR SpiceLine Vhigh=15V Vlow=0V
SYMBOL Digital\\xor -144 704 M0
SYMATTR InstName A4
SYMATTR SpiceLine Vhigh=15V Vlow=0V
SYMBOL diode 512 624 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName ZD1
SYMATTR Value ZID
SYMBOL Digital\\buf1 0 736 M0
SYMATTR InstName A3
SYMATTR SpiceLine VHigh=15V Vlow=0V Td=350n
SYMBOL bv 96 784 R0
WINDOW 0 46 54 Left 2
WINDOW 3 24 96 Invisible 2
SYMATTR InstName B1
SYMATTR Value V=7.5+7.5*SGN(V(PMOD))
SYMBOL res 800 96 R0
SYMATTR InstName RESR
SYMATTR Value 1p
SYMBOL current 944 256 R0
WINDOW 0 40 34 Left 2
WINDOW 3 24 80 Invisible 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName ILOAD
SYMATTR Value PULSE(8 8 0 100n 100n 1m 2m)
SYMBOL cap 512 512 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 100n
TEXT -424 928 Left 2 !K1 LP LS 1
TEXT -424 976 Left 2 !.MODEL DID D(Ron=10m Roff=1E7)
TEXT -424 952 Left 2 !.MODEL MSW SW(Ron=10m Roff=1E7 Vt=7V5)
TEXT -424 1024 Left 2 !.LIB OPAMP.SUB
TEXT -424 1048 Left 2 !.tran 0 50.1m 50m 10n uic
TEXT -424 1000 Left 2 !.MODEL ZID D(Ron=10m Roff=1E9 VRev=1V)
LINE Normal 416 224 416 144 2
LINE Normal 432 224 432 144 2
Again copy and save as an .asc file then open with LTSpice. I have transferred the values from my, broken, program, into it.

Right click on bits. In particular the MODULATOR, A1, is set for

Mark=160K Space=220K

B1 turns its output into digital things

V=7.5+7.5*SGN(V(PMOD))

The DFLOP, A2, does a divide by two to give FMIN/FMAX as 80K and 110K.

BUFFER, A3, in association with XOR, A4, gives the dead time

VHigh=15V Vlow=0V Td=350n

U1 is the 'error amplifier'. It's output is clamped by ZID. The compensation is 'rubbish'.

Two pictures. 1A Load and 8A Load. Yes... it appears to work but you might like to make its life harder and it will fall to pieces.

The 8A Load includes the Resonant Capacitor current. 3A RMS. The program based on the APP Note sums suggested 2.8A RMS. The sums are 'approximate' but as a check for rationality it seems things are close enough.
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File Type: png Screenshot at 2017-11-25 15:30:33.png (18.2 KB, 88 views)
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Old 26th November 2017, 12:04 PM   #12
TroelsM is offline TroelsM  Denmark
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Thanks a lot for taking the time to do this!

I tried to load the file in LTSPice and it works. You have great skills in simulating.
One interesting thing is that the voltage on primary bus will drop a lot if the mains voltage is low and the mains cap is small. I measured down to 200V in my test-setup. That drives the primary-current up if output regulation is to be maintained.

I think that the next step with the current prototype is to verify whether the primary current actually rises above the saturation-limit or if I have another limitation somewhere.

TroelsM
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Old 27th November 2017, 02:47 AM   #13
MorbidFractal is offline MorbidFractal
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Quote:
Originally Posted by TroelsM View Post
Thanks a lot for taking the time to do this!

I tried to load the file in LTSPice and it works. You have great skills in simulating.
Thanks. My model still has mistakes. In particular the range I have set for the Modulator. Fmin can probably go lower. Check the OnSemi APP Note. Fnom, 395V, might be 80K but to get regulation down to 350V you have to set a lower value for the Modulator. Try their linear model to see how far down you can go before you hit Non-ZVS... drop of the left side of the peak. Again my compensation scheme is rubbish.

I should say Thank You for pointing me at that particular application note. I have looked at these things in the past and got nowhere.

In respect of Spice, for me, KISS works, especially for SMPS. Use the simplest bits to approximate what you have so you can have a chance to see what might be going on without hitting non-convergence errors in A when the problem was in Z. Sometimes you still have to tweak A a bit.

Quote:
One interesting thing is that the voltage on primary bus will drop a lot if the mains voltage is low and the mains cap is small. I measured down to 200V in my test-setup. That drives the primary-current up if output regulation is to be maintained.
Stuff like that happens. You should really check it out.

Your input bulk capacitor will charge up to 1.14 x RMS input voltage. Then it discharges as your power supply sucks current out of it. If you assume a constant current then dV/dT = i/C over 50mS if you are at 50Hz. Something like that.

Google/Wikipedia?

Quote:
I think that the next step with the current prototype is to verify whether the primary current actually rises above the saturation-limit or if I have another limitation somewhere.

TroelsM
The OnSemi APP Note gives you a sum to estimate your minimum primary turns. I went off in a box elsewhere but it assumes a sinusoidal voltage drive and that would appear to be valid.

Flux excursion is integral of volt-seconds. Typical ferrites can be operated up to 300mT. Look at the Siemens/EPCOS data sheets. In this sort of converter, other than under transient conditions, the flux excursion is symmetrical about 0 so your base figure, dB, might be 600mT, +/-300mT.

It's reduced because you run into Core Loss Limitations. Again the Siemens/EPCOS data sheets give you graphs... of Pv/m^3 for various operating frequencies and, half, flux excursions. You also get tables for various cores giving thermal impedance for passive cooling fully wound.

Seriously... Rather than using a bit of junk from an old ATX supply. Think about dropping some money on your local electronics supplier to buy something you can design with.

Just for the fun of it I went overboard. LCC resonant. 350 in 60V out. 1A/8A transient. You will not get to know. Meh.
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Old 28th November 2017, 10:35 AM   #14
TroelsM is offline TroelsM  Denmark
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Found another app-note that deals with the transformer in a different way.

Page 12:

http://www.ti.com/lit/ug/slou293c/slou293c.pdf

I (think I), understand why this winding-scheme can give a "better" inductance-ratio, but for DIY it looks more complicated with regards to materials and safety-distances.

Kind regards TroelsM
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Old 28th November 2017, 01:31 PM   #15
MorbidFractal is offline MorbidFractal
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Another excellent find.. .

http://www.ti.com/lit/ug/slou293c/slou293c.pdf

don't forget...

http://www.ti.com/lit/ml/slup105/slup105.pdf

Where Lloyd Dixon, formerly of Unitrode which was bought up by TI, describes and characterises the same technique.

Possibly one thing to note is, once again, where the leakage inductance is located within the transformer/inductor. In the older note it is associated with the outer winding, L1. In the newer document it will again be associated with the outer winding. In this case the secondary windings.

The OnSemi application note mentions that the basic analysis depends on the leakage inductance being associated with the primary. It does go on to propose how the result might be adapted for 'another' case. However I'm not certain how precise or valid the proposal might be. Especially if there is uncertainty as to where the leakage inductance is in fact located.

I have always had some difficulty visualising the actual structure of these things but, and I will probably be wrong, it is not possible to model such things reliably in SPICE using coupled inductors... As a result I would be inclined to follow the method proposed by Dixon and associate the leakage inductance with the Primary. Swap the order given in the newer note with secondaries internal and primary external.

Of course as per the OnSemi note it may be possible to make adjustments. Otherwise you are back into the realms of 'suck it and see', 'cut and try'. Ultimately using the method as described, but swap the winding order, appears to give you the best possibility of designing something that will behave in the way you have designed it.

This may not make the most 'efficient' use of the core or, in particular, winding area but things will remain in a 'comfort zone'. It may be the case that for volume manufacturing it will be worthwhile to shave costs by playing dirty but you may invite hidden consequences. It would appear that most hobbyists end up scratching their heads when things do not work as expected whilst others could claim working solutions but, other than 'look it works', might not be able to claim that the underlying design is robust.

It is not so much that the actual method gives a better inductance ratio. More importantly it gives a relatively predictable and calculable inductance and inductance ratio... perhaps +/-10%. If you want to play dirty then you might achieve better for the same core/bobbin for various definitions of better.

In respect of DIY and in particular Agency Requirements it may 'look' more complicated. In respect of volume manufacturing it is all much of a muchness. Either way there are more than a few ways to simplify your design. The major one for a hobbyist will be the use of triple insulated wire, TEX-E

In the TI design they mention 3.2mm spacers. This is for creepage/clearance of 6mm and would, in old days, have been implemented using 'margin tape'. With TEX-E the 'problem' goes away.

Also the TI design uses one row of pins for primary terminations and the other row of pins for secondary terminations. Again this is for isolation.

I have attached a picture of an ETD39 bobbin, as used in the TI example. Left is Original and Right is Modified. Pin spacing is 5.08mm. By chopping out two of the pins I have achieved in excess of the required 6mm creepage/clearance distances.

Basically you aim to terminate/wind/terminate from one side of the bobbin to the other side with no returns and connect on the board. Two Primaries, 4 pins. One Primary Auxiliary, 2 pins. Two Secondaries, 4 pins. Two Secondary Auxiliaries, 4 pins.

TEX-E for the primaries and auxiliaries. As you have previously noted you might wish to associate the auxiliaries with the secondaries for the purpose of regulation. The TEX-E lets you do that, in particular for the primary one, without having to worry too much about isolation requirements.

Other logistics may or may not apply. The trick is to consider the possibilities based on what you have available and work to keep things neat... otherwise place the lumps where they have less impact.
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Old 1st December 2017, 07:33 AM   #16
TroelsM is offline TroelsM  Denmark
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Hi.

As for the 6mm spacing: I have disassembled a lot of ATX-transformers (NOT LLC) and quite a lot of "winding-volume" is wasted in these due to the "spacing-tape" that is used in the end of each winding to get the creepage/clearance.

On the other hand when I see pictures of commercially available LLC smps for audio there is no sign of this spacing-tape, the windings are often side-by-side, and apparently they get the creepage/clearance just with the transformer-bobbin having the spacing and grooves placed strategically.

This is one of the things that attracted me about LLC: the option for huge creepage/clearance with relatively simple and diy-friendly things.

99% of all ATX-transformers have vertical center-leg and the ETD39 you show have the centerleg horizontally. The latter option are probably preferable as the terminations of pri and sec goes to opposite sides of the bobbin.

As for why to this for diy: certainly not for the money. The complete 500W LLC units are pretty cheap, and compared to the time/cost of making just a simple working LLC-prototype the diy-rute is ONLY for the fun (and the challenge :-) )

Kind regards TroelsM
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Last edited by TroelsM; 1st December 2017 at 07:42 AM.
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Old 1st December 2017, 10:11 AM   #17
TroelsM is offline TroelsM  Denmark
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Figure 9 on page 8 in An-18 shows "offset windings" that are not recommended in that application, but wouldn't it potentially be very useful in diy LLC?

Kind regards TroelsM
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Old 1st December 2017, 03:15 PM   #18
voltwide is offline voltwide  Ireland
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Quote:
Originally Posted by TroelsM View Post
Hi.

As for the 6mm spacing: I have disassembled a lot of ATX-transformers (NOT LLC) and quite a lot of "winding-volume" is wasted in these due to the "spacing-tape" that is used in the end of each winding to get the creepage/clearance.

On the other hand when I see pictures of commercially available LLC smps for audio there is no sign of this spacing-tape, the windings are often side-by-side, and apparently they get the creepage/clearance just with the transformer-bobbin having the spacing and grooves placed strategically.

This is one of the things that attracted me about LLC: the option for huge creepage/clearance with relatively simple and diy-friendly things.

99% of all ATX-transformers have vertical center-leg and the ETD39 you show have the centerleg horizontally. The latter option are probably preferable as the terminations of pri and sec goes to opposite sides of the bobbin.

As for why to this for diy: certainly not for the money. The complete 500W LLC units are pretty cheap, and compared to the time/cost of making just a simple working LLC-prototype the diy-rute is ONLY for the fun (and the challenge :-) )

Kind regards TroelsM
agreed.
To answer an old question: The resonant frequency of LLC circuit is constant and independent of load.
The q-factor varies with load.
And yes, I use special sectional bobbins as you described above.
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Old 1st December 2017, 03:27 PM   #19
voltwide is offline voltwide  Ireland
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Concerning catastrophic turn-on failures:
At the first moment the secondary is shorted by the bulk caps.
To avoid excessing primary current flow, the clock frequency should start far above series resonant frequency.
Most controllers provide a softstart feature to accomplish this.
Be aware that without a current limiting, short circuit at a clock frequency close to series resonant frequency will blow any primäry MOSFET - this is the well known resonant catastrophic case.
The LLC is per se NOT short circuit proof.
There are cycle-by-cycle overcurrent protection features implemented in various controller chips, I cannot comment on these.
My preferred current limiting solution are 2 diodes clamping primary resonant voltage to the power rails. This has proven rock solid in practical applications and does not require a soft start.
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Old 2nd December 2017, 01:03 PM   #20
TroelsM is offline TroelsM  Denmark
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I'm not sure I understand how the diode-clamps should be connected, - or how it should work. Any app-note about it? - any ideas on how big the ratings for diodes should be? MUR340 (3A/400V)?
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