PSUD (Power Supply Unit Designer)

> And BTW, FWIW, FIY: I just discovered a "buglet". I discovered the the results panel can be re-sized (another thing I didn't find over the years). Good! BUT when I resized it to zero (to emphasize the curves), it won't come back! And does not heal on re-start.
Attached image shows the resize cursor doing nothing. Cellfone shot because Windows screen-grab did not show cursor.
Obviously I will fix that by deleting the program and installing a new copy (or beta 6). So don't even look at it. But if you re-use this panel code in III, it is something to look into.

When I enlarge the plot area to max, and then hover the mouse over the edge of the plot panel, the mouse still changes to the panel edge icon and I can then push the plot panel back to see the results panel again - I'm using Ver 2.1.0 Build 59.
 

PRR

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> using Ver 2.1.0 Build 59.

Ah, then this may have been fixed already; I've got 2.0.4 - 43. Will pull a newer copy.

EDIT-- 2.0.4-43 is the last version on the Download page.

Un-Installed (quick!) and installed fresh- yes -43 and yes the result panel comes up zero-width (is there a lingering setings file?) and will not resize.

Un-installed. Got beta 2.1.0-60. Looks different. Panel came up zero-width but DOES resize. Graph is now white? Auto-Run!! But graph colors different every run? (This echos TSC.) Will play.
 
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Thinking dummy-users: once a voltage and current have been specified you "can" compute VA and estimate a % (30% for <10VA, 5% >100VA). This will not be right for all parts! But it might avoid a recent case where a default winding R was way-way inappropriate, and it was not clear from how the user described the problem.

This is a brilliant idea, it could be handled by better training and form layout on the transformer screen. The help system is undergoing a large overhaul to up the level of detail. We've moved on in 19 years, I might do a series of Youtube videos to start off easy then move onto more complex scenarios. {i134}

Also the capacitor ESR can be ballparked from uFd (primarily, V as a secondary correction) (V got from PT ACV and 1.4 or whatever plus a fudge). 2 Ohms may be good for 40uFd(?) but is way-wrong for 50,000uFd.

Agreed. I will get the software to "suggest" a value for ESR when the capacitor is changed in a beginner mode. The software will have four modes {+i158}:

  • Beginner. Things like ESR and %regulation are displayed but worked out automatically. No user intervention possible.
  • Designer. Items are now manually set but "suggested". Range checks on inputs to sanity check information and query the user input. For example, 2ohm 50,000uF gives "are you sure? Likely range is 0.01 to 0.1 ohms" or similar message.
  • Advanced. Probably what most people on here would want. All settings are manual as they are now. Rectifier creation tool enabled, etc.
  • Debug. Inaccessible unless you get a one time code from me to liven the features up. Saves me having to compile a debug version of the software and send through the mail. Deliberately made difficult to access without one to one backup from me as these things (in the wrong hands!) can fill the hard disk up fairly quickly and cause more problems than they solve...
On this note, does anyone have a list or spreadsheet of typical ESR against capacitance value? I could go through some catalogues and make one up but don't want to re-invent the wheel if someone has one out there already :D

Preserve user inputs when not stupid. "k" may be proper but "K" should not raise complaint.

Agreed {+i159}

And it bothers me when 50,000uFd comes back as 50mFd-- I don't think that way (actually remember when uFd was spelt mfd).

Yes, I also remember mfd being "microfarad" I'm sure it was used in the US more than anywhere (I learnt a lot of my trade out of old ARRL handbooks :D). Here's a potential improvement where a config option could be set {+i160}:

  • Have 10^3 steppings (pF, nF, uF, mF, F) as we have now e.g. 470nF
  • Lock to uF e.g. 0.47uF

Agree that NTC modeling opens major headache. Useful and currently fashionable, but not worth effort IMHO. Design the supply to bang-start without blow-up, then add the NTC as refinement.

NTC is simply not do-able within the confines of PSUD because of all the thermal modeling and environmental conditions (i.e. what's around it, ambient temperature, reflective surfaces, etc.) A soft start is something that will go in though as I know a lot of HV power supplies have this kind of thing in. So it will be an approximation rather than a direct model. {i136}

Audio range output impedance is, for practical purpose, the output cap. As you say, if more detail is needed, the user probably should be on breadboard.

Agreed (or on a SPICE based system which is more suited to this type of design concern).

In past a fair number of others, told to "PSUD!", say "Mac!". Of course now they say unix or ChromeBook or Android. Can't please everybody. HTML4 may be the most universal going-forward, but I have no idea what that would involve.

Doing the Mac, Unix, Android versions is now much easier with the tools I'm using. The HTML thing more difficult, I'm not ruling any of these things out but there are other items higher in the food chain that would need to get sorted out first. Are emulators like Virtualbox available for the Mac? All the user would need is a nice old copy of Windows 2000 and PSUD would happily chug along ;)

And BTW, FWIW, FIY: I just discovered a "buglet". I discovered the the results panel can be re-sized (another thing I didn't find over the years). Good! BUT when I resized it to zero (to emphasize the curves), it won't come back! And does not heal on re-start.
Attached image shows the resize cursor doing nothing. Cellfone shot because Windows screen-grab did not show cursor.
Obviously I will fix that by deleting the program and installing a new copy (or beta 6). So don't even look at it. But if you re-use this panel code in III, it is something to look into.

This is one area which is going under a lot of rework right now. There is a new option on it to AutoResize which makes the table exactly the right width for the items within it {i101}. However you want it smaller not bigger so I will put "hide" buttons on this panel to give you more screen real estate for the charts {+i161}.

And thank you thank you thank you!

You are welcome :)

ps: if you are wondering what all the items are in curly brackets, i = incident so {i101} is an incident I've already captured or dealt with, {+i161} is an incident that has just been captured as a result of this conversation. You may see a {-i999} minus red one which is something that was captured and turned out that it wasn't possible for one reason or another.

The change log in the help file (another new feature!) shows these numbers so you can see if they came in with each release of the software.
 
But graph colors different every run? (This echos TSC.) Will play.

Yep this is pretty poor. PSUD3 will auto-pick colours (except that awful bright yellow which is all but invisible), users in Designer or Advanced mode will be able to change colours and chart widths.

With the new file format it will be able to save this information so it will carry over from session to session {i120,i121}
 
If too much detail is not needed, would it be possible to demonstrate impedance of the final cap using formulae like one could use with a calculator? Just a thought/wish!

This won't be possible as within PSUD there is no concept of inductance in either the capacitor or the wiring. Both of these would affect the output impedance of the power supply and without them the results would be meaningless (or more likely misleading).

SPICE based tools are much better suited to this kind of design need. {-137}
 
duncanamps said:
There is a 220mΩ resistor between the two but only 567.85mA flowing through it, for a difference of nearly 60V? At this point Mr. Ohm and Mr. Kirchoff would be scratching their heads. As am I.

The fact that the power supply is modeled with unrealistic / inappropriate values should not change the fact that this should not happen. The internal checks in the software should pick up on this and they don't.
Somewhere in a thread on here I saw a PSUD2 screen grab which had a similar problem, although less obvious. I think it was a CLC supply. The difference in average voltages across the two Cs was about a factor of 2 different from the average voltage across the L; that nice Mr. Kirchoff says these two values must be equal. Big snag is that I can't remember which thread it was! The difference was too big to be simply rounding error - it was something like 7V vs. 12V on a 300V supply. Is it possible that this could be caused by the step size being too large? Or the calculation thinking it has converged when it hasn't quite made it. My experience with numerical calculation is that it can be quite difficult to automatically determine when adequate convergence has been reached.
 
This won't be possible as within PSUD there is no concept of inductance in either the capacitor or the wiring. Both of these would affect the output impedance of the power supply and without them the results would be meaningless (or more likely misleading).

SPICE based tools are much better suited to this kind of design need. {-137}
Understood! Nevertheless, it seems there will be major upgrade to an allready great tool! Thank you very much:)
 

PRR

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> a config option could be set {+i160}:
> Lock to uF e.g. 0.47uF


My 1000uFd/mFd was just an example.

My thought was "preserve user input". The internal representation is probably 1EE-3 anyway, so hold the user-input as a verbatim text string. If I type "50,000,000,000,000pFd" which a saner person would call 50uFd, and the code would call 5EE-5; but _I_ typed 50,000,000,000,000pFd for some human-specific reason.

OK, this does lead to entry-box and schematic display issues.

Obviously "69 cats" can't be sensibly parsed and should be thrown back at me. But inappropriate, wrong-case, or spaced-out user entries should be tolerated and stored for display. (I HATE those VISA # boxes that barf on spaces. Humans need the spaces for eye-control. Computers can discard spaces real quick. Why am I working to the computer's convenience?)

> Virtualbox available for the Mac? ...copy of Windows 2000

Vbox, yes. While W2K is widely available cheap-cheap, the users I have known may not want to scrounge CDs off eBay, or have never installed an O/S. Vbox is learning-curve. Not "instant gratification".

Dislike yellow on white.

_I_ would give Red for first value selected, Blue for the next, and some sensible more choices for clutterers.

Might also pre-select the rightmost element (R or I) for display, as the most-likely plot of interest. OK, maybe an option, so I can skip it when I am deep in winding RMS comparisons.
 

PRR

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Joined 2003
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> impedance of the final cap using formulae like one could use with a calculator?

It is not "one simple impedance". Or rather it is a capacitive impedance with stray parasitics. It would plot over audio frequency as a slant-line, leveling off sub-sonic for leakage, and super-sonic for ESR, and generally rising in HF with likely a dip. You have a calculator (in hand, in PC, or on-line), which will quickly give values for a few frequencies. In practice we don't try to know ALL the quirks of the Z curve, so long as we know it "does not matter for practical purpose".

It also does not come-from the computational path PSUD uses (time-stepping). It can be derived, but that leads to a nearly all-purpose program. And that has been done. And is overkill for most audio "Z out" questions.
 

PRR

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> typical ESR against capacitance

No; but I happen to have some transformer VA/regulation data handy. Attached.

Two tables.

The first has notes, and some data for 45 deg C rise working.

The second is for 75 deg C rise, which many users would call "too hot!!" It is more an indication of what a given core "could" do, with a fixed load (regulation unimportant). Most of our stuff will not be worked this hard, or rated for such rise.

Note the difference for EI-100 core in square or near-square stack at 45 and at 75 deg C rise. The cool near-square shows 89% efficiency, so regulation probably near 10%. Regulation be dammed, let it run hot, 1.6X the power and 15% regulation. Very nearly the same power source, but re-rated to run too hot to touch.

I *think* I have seen a curve VA/reg, but not finding it now, and would have to be tweaked away from extra-hot designs.

For more fun: when you face small windings at 700V(CT), the "optimum" wire size is too small for rapid winding. We sometimes see these with lower DCR than you would expect from line and heater DCR-- they upped the HV wire size to speed production.

We can't get a spot-on guess, of course. But it may help to not use 31 Ohms for a wee little lump with hundreds of Ohms inside.
 

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> impedance of the final cap using formulae like one could use with a calculator?

It is not "one simple impedance". Or rather it is a capacitive impedance with stray parasitics. It would plot over audio frequency as a slant-line, leveling off sub-sonic for leakage, and super-sonic for ESR, and generally rising in HF with likely a dip. You have a calculator (in hand, in PC, or on-line), which will quickly give values for a few frequencies. In practice we don't try to know ALL the quirks of the Z curve, so long as we know it "does not matter for practical purpose".

It also does not come-from the computational path PSUD uses (time-stepping). It can be derived, but that leads to a nearly all-purpose program. And that has been done. And is overkill for most audio "Z out" questions.
OK. I had to read this many times but I think I got it. Thanks! Now, given the chance, I would like to ask something. So far, when using PSUDII I try to achieve a voltage plot with a as sharp and clear as possible roll off thinking that this means low Z out(see pic). Actually not my thinking. There is a paper somewhere on the net about it - unless I haven't understant it correctly. I come to think that this approach is not right. I would like your opinions on this please.
 

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PRR

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If we want to talk about program USE, this should probably be split into another thread, not clutter the wish-list discussion. (Mod?)

> as sharp and clear as possible roll off thinking that this means low Z out

No. It is perfectly possible to have a HIGH audio impedance with very low ripple and sag.

> There is a paper somewhere

Must be more qualifications on that statement.

Let's try a big L and no C... well big L and small C.... ....uh, PSUD hates to do that. It ran 2pFd last cap but hit Time Step error; 100pFd popped a box "0.001u...{or more}". (So why didn't 2pFd barf pre-run?)

Fairly basic if extravagant DC filter, ending with 250H+30r and 1nFd+200K(!) loaded in 5K. By dirt-sketch, taking C2 as "huge" (lo Z), the output impedance sketches like:

Freq __250H __1nFd+200K ___Zout
_20Hz__ 31K ________ 8M ___ 31K
200Hz__310K ________ 1M ___236K << resonance near 300Hz!
_2KHz__3.1M ______ 280K ___257K
20KHz__ 31M ______ 208K ___207K

A "low Z" power source for a 5K load might be 1/10th load, <500r. Here the audio-band Zout is like 50X the load! Yet the ripple is teeny (41uV).

Comparing 5K load to 50K load and running to asymptote.... uh, I have found an oddness. But by inspection, the DC impedance is near 100 Ohms (31+30+30+waveform).

On _your_ plan, assuming I1 is zero then 50mA, and shows a 5V drop, the DC output impedance is 5V/0.050A or 100 Ohms. (But this can not be right?) The audio-band output impedance is dominated by 60uFd, which a good audio Reactance Chart will tell you is 133r @ 20Hz, 13r @ 200Hz, 1.3r @ 2KHz, and probably ESR limited and also moot above that. (2m seems unlikely?)
 

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@PRR; Thanks for response. Your explanation is very much appreciated!
@Mods; By no means is my intention to hijack this great thread. And I don't think I could tell something important on a new thread. Let's keep it as a small parenthesis.
@Duncanamps; Good thing to have the "beginers" button! Perhaps a "beginers audiophile" button too?:D
 
Duncan, can you please clarify your to do item 122 "Add 'R' type block, just a resistor only".

Does that allow a resistive load to be inserted along a ladder circuit (as per inserting a C, RC, LC, or current tap in PSUD2)? That would be helpful for simulating power up conditions within an amplifier that has various bleed or pre-load resistors along the B+ supply distribution (before valve stages start to load parts of the DC distribution).
 
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OK. I had to read this many times but I think I got it. Thanks! Now, given the chance, I would like to ask something. So far, when using PSUDII I try to achieve a voltage plot with a as sharp and clear as possible roll off thinking that this means low Z out(see pic). Actually not my thinking. There is a paper somewhere on the net about it - unless I haven't understant it correctly. I come to think that this approach is not right. I would like your opinions on this please.
What is causing the step in voltage @ 10seconds?
 
What is causing the step in voltage @ 10seconds?
It is a stepped load (current tap) to see how it reacts. Novice approach... I think it's better to move it in a new thread after all. I don't feel comfortable destructing all those scientists from contributing to the development of this software. I wish I could do so! But I can only speak the voice of all us non EEs for who the PSUD is our desert island software! :)
 
Duncan, can you please clarify your to do item 122 "Add 'R' type block, just a resistor only".

The request was from one of the beta testers to allow current limiting for HV supplies by putting R on its own just before the load. After mulling this over, I may not even proceed with it as it's a very niche requirement that would be useful to a very small number of people.