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Wave Field Synthesis Project
Wave Field Synthesis Project
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Old 27th July 2018, 05:49 PM   #21
altie is offline altie
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And cool project btw. I hope it takes off.
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Old 27th July 2018, 08:57 PM   #22
bobthedespot is offline bobthedespot  United States
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Wow awesome idea on the Audia products. Never would have guessed to search for that...

Cobranet is a great protocol that would put me closer to end game with the synchronization stuff...

PM with what you are selling, I'll try to make a fair offer!
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Old 28th July 2018, 02:23 AM   #23
altie is offline altie
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PM sent.
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Old 28th August 2018, 06:39 AM   #24
HydrocarbonPrimate is offline HydrocarbonPrimate
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Quote:
Originally Posted by bobthedespot View Post
Found a source for es9018 DACs that will run me $4 per channel. That is the plan unless someone knows of a serious problem with that chip.

The current plan for feeding the DACs is m1000e --> AES67 CAT5 ---> Alterra FPGA (tbd) --> I2S ---> 9018 DAC ---> Phillips TDA 8598 amps

A few more questions about this:

1. How concerned should I be about global clocking these DACs? Is that possible? I have zero experience with word clocks, or anything like that. Would that appreciably improve the sound?


2. If I want to minimize distortion from these chip amps and preserve the headroom of the amp, should I consider adding a dummy load in series with the speakers? I think that noise for this amp is pretty nasty at low levels, but the performance is pretty good right before saturation.


Any other comments or criticisms are welcome.



just looking at this interesting project, a search for those
DACs comes up with numerous things. Would it not be more cost effective to build a set of custom (but simple) boards for interfacing with the FPGA you could possibly put DAC chips and amp chips on the same board(s).
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Old 28th August 2018, 02:23 PM   #25
JonFo is offline JonFo  United States
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Sounds very cool, has this project progressed to implementation yet?
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Old 6th September 2018, 11:51 AM   #26
bobthedespot is offline bobthedespot  United States
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To some extent, yes.

I have tested 6, 8, and 12 driver subsections with apparent success.

Right now, I am building an entirely new set of DACs and AMPs. Unfortunately you can only achieve 0.7 cm spatial resolution with a sample rate of 48kHz before ringing becomes audible, and that just isn't enough to generate the types of wavefronts I want from a straight array with 34mm spacing. Furthermore, a computer can only connect a maximum of 128 USB devices, and I definitely don't want to run into issues there. Each hub counts as its own device, and I still haven't settled on a hub that never drops packets (without costing wayyy too much). I may have to build the usb host myself, which is certainly possible.

With these considerations in mind, I have switched to building 10 channel USB DAC/amp modules. Each board will have one usb device with 10 I2S outputs, and 10 channels of amplification.

Right now I'm testing at 192kHz/32bit and the results sound much better than 48kHz/16bit.

I am still trying to choose the right amp for the project. Any tips? I definitely don't need more than 5-10 watts, but I'm open to over-engineering. Noise from the amp is going to be a significant factor no matter what choice I make, given the sheer number of channels.

Since I would like to save money on the power supply, I have been thinking I would use just one supply for all of the boards. Maybe that would be an issue for a Class D topology?
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Old 13th September 2018, 12:34 AM   #27
SmarmyDog is offline SmarmyDog  United States
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Just because the sample rate is 48kHz doesn't mean you cant use a higher resolution (e.g., 1MHz) delay buffer prior to sending the data/clock to each DAC to time-shift in uS increments.
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Old 13th September 2018, 01:59 PM   #28
bobthedespot is offline bobthedespot  United States
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SmarmyDog,

Can you elaborate on this? I thought that I would need a Whittaker-Shannon interpolation filter to delay all frequencies without any phase errors.

I'm woefully under-educated in this specific field...

bob
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Old 13th September 2018, 02:05 PM   #29
Sabbelbacke is offline Sabbelbacke  Germany
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I assume he is talking about the minimal time-resolution for processing/output-latency or the minimum delay step on the output.
Staying int the 48kHz Domain and processing it at the same frequency has you stuck to this time-domain and max freq range (nyquest) - but transforming the 48kHz signal into a faster processing matrix enables you to shift or delay the signal finer than the 48kHz would normaly provide. Of course frequency resolution isnīt improved by this step - 48kHz should suffice for what you want.
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Old 14th September 2018, 02:44 AM   #30
SmarmyDog is offline SmarmyDog  United States
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Yes, just the simple variable-depth FIFO buffer for the data/clock stream prior to conversion for each driver. Perhaps an exercise in diminishing returns though.
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