The reason an ASRC is used for jittter reduction of SPDIF is basically because some ASRC chips have a good PLL which generated a new better clock than the clock from the DIR.
If I will create a mainboard the SPDIF part will not be part of it, both options are possible, maybe even selectable (if I would ever add SPDIF, because at this moment I have no SPDIF source of interest)
If I will create a mainboard the SPDIF part will not be part of it, both options are possible, maybe even selectable (if I would ever add SPDIF, because at this moment I have no SPDIF source of interest)