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optical SFP multichannel transport
optical SFP multichannel transport
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Old 3rd September 2019, 07:15 PM   #11
phofman is online now phofman  Czech Republic
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How does a reclocker work without the original clock to time the reclocker?
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Old 4th September 2019, 08:12 AM   #12
lcsaszar is offline lcsaszar  Hungary
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Quote:
Originally Posted by Asasl View Post
No PLL on remote devices will be used. The master clock is transmitted in the common TDM stream
Hi, In that case you will need a PLL in order to recover the clock from the data stream.

I worked on optical telecommunication (PDH and SDH networks), and your idea seems realizable. What you want to realize is called time division multiplexing. In the TDM technology the individual data streams (for telephony they are 64kb/s) are multiplexed in E1 (T1 in the US) frames, 2048kb/s, and then E3 and up. For audio, you can start from E1, and multiplex 16 x E1 to get 34Mb/s, this will make 8 stereo channels. Or you can go higher, by multiplexing 4 x E3 to get an STM-1 (140Mb/s).

I don't think any error correction is necessary. You can use MMF (multi mode fiber) for domestic short distance use.
I am not sure about the SFPs support any bitrate. You can test a pair and then go further.

Are you planning this for studio use as a commercial product?

I can tell you that an audio CD playback chain has much similarities with telecommunications optical networking. There is laser, sliding window, PLL clock recovery, elastic buffer, jitter issues, etc. Most design and measuring techiques are common in both.
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Old 4th September 2019, 08:17 AM   #13
phofman is online now phofman  Czech Republic
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Basically faster toslink with more payload :-)
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Old 5th September 2019, 04:55 AM   #14
xx3stksm is offline xx3stksm  Japan
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optical SFP multichannel transport
I'm sure the most critical factor in recovering an accurate clock from the incoming stream by FPGA is "continuous clock." SPDIF, which doesn't have "continuous clock," is commonly used in an audio application but not optimum for DSM, where low jitter clock is mandatory. That's why ESS has an internal ASRC for its SPDIF input. SPDIF has "burst clock" only at the preamble for clock recovery. I would say "burst clock" is old school technology mainly used in an analog system like old TV standard, NTSC and PAL. If you want to use FPGA for clock recovery and digital interface at the remote side, the continuous clock must be interwoven in a bitstream. "Burst clock" entirely isn't familiar with FPGA. If you can't have such bitstream, ASRC is the second option. My audio chain employs FPGA for clock recovery from the optical interface. Optical doesn't mean SPDIF(TOSLINK), but phase modulation, where the continuous clock easily can be interwoven.
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Old 5th September 2019, 07:20 AM   #15
lcsaszar is offline lcsaszar  Hungary
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Exactly. Here are some useful links about clock recovery from the E1 (HDB3 encoded) bit stream:

Clock recovery - Wikipedia

HDB3 - clock recovery???? | Electronics Forums

You need to calculate how many channels, what data rate and what bit depth can you transmit at 2048 kb/s. A mono 24 bit 192kHz signal is 4.608MHz in itself, that will not fit in E1. Probably you need to go higher and create your own specific frame structure. But then you will not be able to use any commercial chips, you will need to write the FPGA code yourself.
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Old 12th October 2019, 08:09 AM   #16
Asasl is offline Asasl
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The PCM frame structure will be its own. I cited the picture above. The clock will not be restored, but taken directly from the frame. I will do the project not commercial, but open.
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