I'm working on a DSP board for the rPi, using the ADAU1701 DSP from Analog Devices. The goal is to use the RPi's I2S stream to get audio into the DSP. The crux of the problem is (of course) the MCK. I was hoping to use the pi to generate MCK for the 1701, thinking it would be synchronous with the I2S clocks and data. The 1701 can take an MCK of 64*Fs, so I generate a clock of 3.072 MHz for Fs = 48 MHz, using pigpio "minimal_clk".
The first issue is that the generated MCK does not appear to be exactly 3.072 MHz (maybe this isn't possible?) I measure the MCK to be about 3.09 MHz. Does anyone know if the exact frequency of 3.072 MHz can be achieved? Of course integer divisions of the rPi clock won't be good enough, but with fraction division and ?MASH? this might be possible.
The second issue is that the generated MCK does not appear to be synchronous with the I2S clocks. I'm using the device tree overlay for "hifiberry-dac" (and it's been tested with pHAT DAC to ensure correct I2S streaming). The hope was that MCK would be synchronous with the I2S BCK and LRCK, where each LRCK (48 kHz) transition would contain exactly 64 MCK cycles. When I scope up the generated MCK and I2S clocks, it is apparent they are not synchronized and drift from each other.
Perhaps the architecture of running the DSP from an rPi generated MCK can not be made to work and I need to use a DSP with sample rate converter or (*gasp*) use a simple DAC to convert the the pi audio into analog and redigitize with the 1701. Another thought was to run the 1701 from an independent crystal oscillator, and have it initiate I2S transfer from the pi, generating the BCK and LRCK, and the rPi would be an I2S slave instead of master, but I don't know if this can be done, either.
The first issue is that the generated MCK does not appear to be exactly 3.072 MHz (maybe this isn't possible?) I measure the MCK to be about 3.09 MHz. Does anyone know if the exact frequency of 3.072 MHz can be achieved? Of course integer divisions of the rPi clock won't be good enough, but with fraction division and ?MASH? this might be possible.
The second issue is that the generated MCK does not appear to be synchronous with the I2S clocks. I'm using the device tree overlay for "hifiberry-dac" (and it's been tested with pHAT DAC to ensure correct I2S streaming). The hope was that MCK would be synchronous with the I2S BCK and LRCK, where each LRCK (48 kHz) transition would contain exactly 64 MCK cycles. When I scope up the generated MCK and I2S clocks, it is apparent they are not synchronized and drift from each other.
Perhaps the architecture of running the DSP from an rPi generated MCK can not be made to work and I need to use a DSP with sample rate converter or (*gasp*) use a simple DAC to convert the the pi audio into analog and redigitize with the 1701. Another thought was to run the 1701 from an independent crystal oscillator, and have it initiate I2S transfer from the pi, generating the BCK and LRCK, and the rPi would be an I2S slave instead of master, but I don't know if this can be done, either.
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