JFET model generator

[ripson]

JFET spice model generator

It might be not the most suited place to post it here, but since this is my favorite section in diya and we are exclusively using FETs for amplifications in our projects so I decided to share something that I developed during the weekend and I hope it will be helpful to some of you.

Before I build an amp I like to simulate it first, and often I need a JFET model with a specific Idss. So I build a simple web-based app that uses some predefined templates and calculates and modifies beta and Vto to get a specific Idss.

Here is the link: JFET calculator <<<<<<<<<<<<<<<<<<<<

Please feel free to share your ideas, improvements, etc...

So how I calculate beta? From the equation below:

beta = Idss/Vto²

How about Vto? It's a bit more complicated:

Unfortunately, Vgs(off) is not exactly Vto, Vgs(off) is a lower value than Vto, actually, I haven't found any specific definition of what Vto is, apart from "Threshold Voltage". Vgs(off) is a Vgs voltage that reduces Id to 0.1uA at Vds=10V. Someone mentioned that Vto might be... Vgs that reduces Id to 1% of the Idss? So I had to get Vto from the transconductance curves from the datasheet... well... roughly.

As Mark Johnson pointed out the above plot is a straight line, but it is on a log scale, to be precise it's a Log-log plot so the dependency between Idss and Vto is a power function: Vto = k * Idss^m - k and m are calculated from points (Idss1, Vto1) and (Idss2, Vto2).

The key to having a reliable Vto is to properly specify these two points that define a straight line in these log scales, for each transistor model (across the range of Idss) there are going to be different points.

For 2sk170 I have chosen:
1) Idss: 1mA, Vto: -0.2V
2) Idss: 10mA, Vto: -0.55V

For 2sk246:
1) Idss: 1.3mA, Vto: -1.25V
2) Idss: 5.6mA, Vto: -2.8V

Idss is specified at particular conditions, like Vds=10V, for higher Vds we get slightly higher Idss. Depending on the lambda we get also different values.

If you have ideas on how to modify other values please let me know. I have also looked into built-in LSK170 (A, B and C) models in LTSpice, but I can't see any clues that lead to a conclusion.

 

[R-K Rønningstad]

What happened to the link?

 

[generg]

What a brilliant idea, good that I saved he website.

 

[Skorpio]

Very interesting

For 2sk170 I have chosen:
1) Idss: 1mA, Vto: -0.2V
2) Idss: 10mA, Vto: -0.55V

For Idss: 10mA, I read Vto: -0.65V

 

[ripson]

What happened to the link?

There was no interest in this so I removed it from the server, it's back now., slightly modified.

now I calculate beta from the equation:


beta = idss / (vto * vto * (1 + lambda * vds) * tanh(vds));

 

[ripson]

m = log(Vto2 / Vto1) / log(Idss2 / Idss1);
k = Vto1 / Idss1^m;


and



Vto = k * Idss^m;

 

[twitchie]

Thank you Ripson!

 

[ripson]

Very interesting
For Idss: 10mA, I read Vto: -0.65V

yes, from the 2sk170 spec Vgs(off) is -0.65V for Idss=10mA (at Vds=10V), but Vgs(off) is not exactly Vto, but at least this graph describes dependency between Idss and Vp

 

[ripson]

Thank you Ripson!

you're welcome


But please note I am not in Analog Devices (LTSpice) programmers head. This is my understanding of how these values might be calculated. If someone knows better how to calculate beta and Vto based on Idss for a particular JFET model please let me know, I will adjust the app

 

[Mark Johnson]

Maybe it is a worthwhile experiment to create a simulation which instantiates a phony baloney JFET whose .MODEL parameters are supplied by >>you<<. Values of the parameters KP and VT (for example) which >>you<< provide.

Then see what number the simulator calculates for Idrain at a Vgs and a Vds and a junction temperature that >>you<< provide. You may be able to deduce what calculations the simulator is making, by studying its output result from five or ten such calculations.

 

[ripson]

During the weekend I will try this reverse engineering approach Finally we will get there Now I'm getting Idss about 10% lower than expected.

 

[generg]

I want to thank you for your work, to have scalable Idss for the j- Fet models is really a great help in my simulations.

:--))

 

[ripson]

my pleasure BTW I am going to add also automatically drawing the transconductance curve, but what is the most important, adjust the calculations, so when we specify Idss... let say 10mA in LTSpice connecting 10V to D and S with shorted S and G we get Id = Idss = exactly 10mA.

 

[Mark Johnson]

Ask circuit designers: what aspect of JFET behavior is THE most important effect to model accurately in simulation? If you had to accept ±30% modeling error in all other behaviors, in order to get ±3% modeling error in (JFET behavior XXX), what's the right choice of XXX?

You might as well focus your energies upon the things that really matter to your customers.

 

[ripson]

What I like in my LTSpice simulations is that they are within 5% of the real measurements so far, including most parameters. And because I do it just for myself (no customers), I can spend a few days matching components just for one amp, also building crazy applications just because I have a great fun of doing it

 

[oreo382]

I just ran a J74 model generated for 13ma and got only 9.5ma checked against my Ltspice jfet test program.Current is measured thru the low ohm resistance,R4.If you want to check you will have to generate a J74 model and replace the jfet included with the program I have attached (its a 9ma model).

 

[ripson]

yes, as described earlier

 

[generg]

I had a similar effect but ripson works on it and I trust in his progress...

:--))

 

[ripson]

I also count on you guys. Maybe someone did it before and knows how LTSpice interprets Vto and beta... As I mentioned in #1 "Please feel free to share your ideas, improvements, etc...". I think I am doing the calculations of Vto and beta correctly, why the Idss in LTSpice is too low... don't know...yet.

 

[oreo382]

Yes,a very useful tool for the diy community.Thank you for your work.