The SIT-3X Amplifier

The birth of SIT-3X: Everything started in the at post #119 https://www.diyaudio.com/forums/pas...-mu-follower-amplifier-build-post6161792.html, in a thread which was originally oriented towards the FirstWatt SIT-2 mu-follower circuit. Along the way, I analyzed the circuit of the FirstWatt SIT-3 and discovered a simple circuit change that performs harmonic cancellation, including odd harmonics! After more analysis, simulations, and bench testing, I saw the posssibility of a very low distortion amplifier with no global feedback. Here are the expected specifications:

  • Output Stage: Source Follower Tokin 2SK182ES SIT + IXYS IXTN40P50 PFET.
  • Choice of front-end stages:
    • Buffered, folded cascode FE with no feedback loop
    • XA25 style FE: requires feedback from FEOut to obtain low impedance output.
  • No global feedback.
  • 25W-50W power output
  • Adjustable cancellation of both even and odd harmonics.
  • THD at 1 Watt, 1kHz into 8 Ohms < 0.02%
  • THD at 25 Watts, 1kHz into 8 Ohms < 0.5%
The "Sit Measurements Mu Follower Amplifier Build" provides important background leading to amplifer design presented here. Since forum members are requesting that the design be completed, I decided it was time for start this thread. In my next few posts I will present the current designs for the output stage, folded-cascode FE, and XA25-style FE. There are still issues to be resolved and parameters to be "tuned", but I think that PCB layout can start.
 
As promised, here are the major circuit modules. I believe that the part numbers are consistent and most component values are reasonable, but some more "tuning" might be required. Some resistors wattages and capacitor voltages need to be specified.

Alternative FETs and BJTs might be used in the front ends, requiring some changes to resistor values.
 

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Good news about the TTC011B/TTA006B. I have also used the TTC004B/TTA004B as mentioned in the original thread.

It should be possible to use the THF-51S, but it will need different bias parameters, and possibly different Vds and Iq to get the best harmonic cancellation. Shouldn’t be too far off from the 2SK182ES.
 
Hot News about SIT3X Harmonic Cancellation

I have made progress in understanding the harmonic cancellation that is possible with both SIT/FET and Schade/FET source followers. The cancellation appears to be a form of feed-forward error correction as shown in the drawing below taken from Bob Cordell's "Designing Audio Power Amplifiers" book. The PFET assumes the role of the S1 difference circuit in detecting the difference between the output and the attenuated input, and the role of the S2 circuit in inserting a correction current into the output. With proper adjustment of the A-pot to the gate of the PFET, the error in the output is minimized. I am think I am close to having the proper equations describing the behavior.
 

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Schade Feedback Harmonic Cancellation

The first image shows circuit analysis that derives the triode parameters for Schade feedback.
The second image show a simulation where the top plots show the dynamic impedance of the load on the input to the circuit. That load is 524R being the parallel impedance of the 1k potentiometer load to ground and 100R+1K load to Vrail. The FFT plots show the effect of the harmonic cancellation. The third image shows the Fourier results for different loads and values of the pot setting.
Given that the SIT3X harmonic cancellation requires a potentiometer load of around 1K, it is not unreasonable to consider replacing the SIT in the SIT3X circuit with an NFET having Schade feedback.
 

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Last edited:
Official Court Jester
Joined 2003
Paid Member
well, as mental exercise and challenge completely logical and justified........ but, if diminutive THD, especially combined with dominant 3rd, what's benefit of using SIT at all?

btw. I can't see nothing wrong with XA25 having OS included in FB loop; if excluded, I don't believe it would be beneficial sound-wise (or different at all), only output offset stability will suffer

again, not disputing anything..... how could I, probably making least reasonable choices all the time :)
 
My plan is to proceed with PCB layouts for the circuits shown in posts #2 and #3. Some components and component values will change, but the overall topology, and hence PCB layout, should be the same. I will soon provide some resistor wattage and capacitor voltage values. Some of the folded cascode BJTs and FETs in the front-end will require small heatsinks.

I encourage the brave forum members to run with there own variants of the circuit(s) as they wish.