You are correct, 150W for both heatsinks.
The fan cooled amplifier I show in post #16 dissipates about 170 Watts per heatsink and provides 25W class-A with about 3% THD.
Looking forward to it, including the math! It's all a good learning, and interesting as well! I like the rigor of having a well defined 'why' for the choices we make on amps.
More Sweet Spot theory
Earlier posts presented the sweet-spot relationship:
Id = A*Vd + C*Vd/RL
where the parameters A and C are computed from meaasurements made with a test jig using a single-ended resistor load topology shown in post #2.
The objective of the next few posts is to show how to apply the sweet-spot relationship to the common-sourcemu follower. There is a notational change in the following posts: the quiescent SIT drain voltage Vd becomes X0 and the quiescent SIT drain current Id becomes I0.
Before presenting the circuit analysis of the mu follower, it is useful to examine the behavior of a single-ended resistor load and a 3-terminal generic load, combined with an amplification device such as a SIT, JFET, NFET, NPN transistor, or triode.
This image shows a simple single-ended common-source amplifier similar to the FirstWatt SIT-1. The maian parameter of interest here is RL, the load impedance on the drain of the SIT, and its relationship to β, the current gain (loss) of the due to the load circuit.
Earlier posts presented the sweet-spot relationship:
Id = A*Vd + C*Vd/RL
where the parameters A and C are computed from meaasurements made with a test jig using a single-ended resistor load topology shown in post #2.
The objective of the next few posts is to show how to apply the sweet-spot relationship to the common-sourcemu follower. There is a notational change in the following posts: the quiescent SIT drain voltage Vd becomes X0 and the quiescent SIT drain current Id becomes I0.
Before presenting the circuit analysis of the mu follower, it is useful to examine the behavior of a single-ended resistor load and a 3-terminal generic load, combined with an amplification device such as a SIT, JFET, NFET, NPN transistor, or triode.
This image shows a simple single-ended common-source amplifier similar to the FirstWatt SIT-1. The maian parameter of interest here is RL, the load impedance on the drain of the SIT, and its relationship to β, the current gain (loss) of the due to the load circuit.
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Generic Load Circuit and Measurement
The first image shows a generic 3-terminal load circuit, and similar expressions for β and RL. Since the circuit is unknown, β and RL are derived from ΔI, ΔI(Rload), and ΔX which can be measured external to the generic load.
The second image introduces a sense resistor Rsen between the SIT drain and the bottom terminal of the generic load circuit, which allows for the direct measurement of ΔI. Unfortunately, that circuit modification will slightly change the load impedance seen by J1.
The third image introduces a sense resistor Rsen, between the top of the generic load and the rail supply. Since the "generic load" is a 3 terminal device, using KCL (Kirchhoff Current Law),
ΔI(Rsen) = ΔI(Rload) + ΔI
thus providing the value of ΔI from AC voltage measurements across Rsen and Rload.
With a 1 Watt amplifier output level, an Rsen value of 0R25 (3 Watt, 1% or better) appears provide enough AC voltage drop to enable accurate measurements with a decent multimeter.
Caveat: All of the above computations for β and RL are based on RMS voltage measurements and are correct only if the load circuit does not introduce significant phase shifts, in which case RL would have to be represented by a complex (reactive) impedance and a totally different measurement approach would be needed.
The first image shows a generic 3-terminal load circuit, and similar expressions for β and RL. Since the circuit is unknown, β and RL are derived from ΔI, ΔI(Rload), and ΔX which can be measured external to the generic load.
The second image introduces a sense resistor Rsen between the SIT drain and the bottom terminal of the generic load circuit, which allows for the direct measurement of ΔI. Unfortunately, that circuit modification will slightly change the load impedance seen by J1.
The third image introduces a sense resistor Rsen, between the top of the generic load and the rail supply. Since the "generic load" is a 3 terminal device, using KCL (Kirchhoff Current Law),
ΔI(Rsen) = ΔI(Rload) + ΔI
thus providing the value of ΔI from AC voltage measurements across Rsen and Rload.
With a 1 Watt amplifier output level, an Rsen value of 0R25 (3 Watt, 1% or better) appears provide enough AC voltage drop to enable accurate measurements with a decent multimeter.
Caveat: All of the above computations for β and RL are based on RMS voltage measurements and are correct only if the load circuit does not introduce significant phase shifts, in which case RL would have to be represented by a complex (reactive) impedance and a totally different measurement approach would be needed.
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Common Source Mu Follower Circuit Parameters
The (simplified) mu follower circuit in shown in the first image below. For simplicity, the actual bias circuit for the mu follower NFET M1 has been replaced by a battery symbol. The circuit on the right is a further simplification where the NFET M1 and resistor Rhi are replaced by the undegenerated NFET M1e. M1 has the transconductance gm at the operating point, but is degenerated by Rhi. M1e has the transconductance gme=1/(1/gm+Rhi), which is the effective transconductance of M1 degenerated by Rhi.
The circuit equations for the schematic on the right are simple to solve, with the results shown in the second image. For the brave, the set circuit of equations and solutions is shown in the third image.
The net result is that we obtain the simple equations:
β = Rmu*gme+1
RL = Rload*β + Rmu
We have multiple ways to compute the values for β and RL:
Circuit Equations using known parameter values. The mu follower NFET transconductance (gm) is dependent on bias current and to a lesser extent the Vds of the NFET. For best results, gm should be computed based on calibration of the individual NFET at the desired values of I0 and Vds.
In-circuit measurements, measuring ΔI based on RMS measurements across either Rmu as in the 2nd image of the previous post, or Rhi as in the 3rd image in the previous post.
I will be continuing this thread with mu follower design approaches and examples. It is taking longer than I expected to get things right.
The (simplified) mu follower circuit in shown in the first image below. For simplicity, the actual bias circuit for the mu follower NFET M1 has been replaced by a battery symbol. The circuit on the right is a further simplification where the NFET M1 and resistor Rhi are replaced by the undegenerated NFET M1e. M1 has the transconductance gm at the operating point, but is degenerated by Rhi. M1e has the transconductance gme=1/(1/gm+Rhi), which is the effective transconductance of M1 degenerated by Rhi.
The circuit equations for the schematic on the right are simple to solve, with the results shown in the second image. For the brave, the set circuit of equations and solutions is shown in the third image.
The net result is that we obtain the simple equations:
β = Rmu*gme+1
RL = Rload*β + Rmu
We have multiple ways to compute the values for β and RL:
Circuit Equations using known parameter values. The mu follower NFET transconductance (gm) is dependent on bias current and to a lesser extent the Vds of the NFET. For best results, gm should be computed based on calibration of the individual NFET at the desired values of I0 and Vds.
In-circuit measurements, measuring ΔI based on RMS measurements across either Rmu as in the 2nd image of the previous post, or Rhi as in the 3rd image in the previous post.
I will be continuing this thread with mu follower design approaches and examples. It is taking longer than I expected to get things right.
Attachments
I believe this wil do as well:
https://images-na.ssl-images-amazon.com/images/I/61XL1bEdfoL._SL1000_.jpg
https://images-na.ssl-images-amazon.com/images/I/61XL1bEdfoL._SL1000_.jpg
DEFiSIT is a Mu Follower Circuit
I performed a similar analysis of the FirstWatt DEFiSIT circuit shown in first image below. The second image shows the simplified circuit which was analyzed. The DEFiSIT is a mu follower with equations very similar those for the common source mu follower.
"Degenerated Transconductance of M1:
gm[M1e] = 1/(Rlo+1/gm[M1])
Mu Follower Current Gain:
β = ΔI[Rload]/ΔI[SIT] = gm[M1e]*(1/gm[SIT]+Rmu) + 1
SIT drain load impedance:
RL = ΔX/ΔI[SIT] = Rload*β + Rmu
Push-Pull Ratio:
ΔI[M1]/ΔI[SIT] = β-1
As a result, the "sweet-spot" condition for the DEFiSIT can be derived from the equation derived in post #10:
Id = A*Vd + B/RL + C*Vd/RL + D
which is fairly well approximated by the equation from post #49:
Id = C*Vd/RL
I performed a similar analysis of the FirstWatt DEFiSIT circuit shown in first image below. The second image shows the simplified circuit which was analyzed. The DEFiSIT is a mu follower with equations very similar those for the common source mu follower.
"Degenerated Transconductance of M1:
gm[M1e] = 1/(Rlo+1/gm[M1])
Mu Follower Current Gain:
β = ΔI[Rload]/ΔI[SIT] = gm[M1e]*(1/gm[SIT]+Rmu) + 1
SIT drain load impedance:
RL = ΔX/ΔI[SIT] = Rload*β + Rmu
Push-Pull Ratio:
ΔI[M1]/ΔI[SIT] = β-1
As a result, the "sweet-spot" condition for the DEFiSIT can be derived from the equation derived in post #10:
Id = A*Vd + B/RL + C*Vd/RL + D
which is fairly well approximated by the equation from post #49:
Id = C*Vd/RL
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DEFiSIT sweet spot calculations
DEFiSIT is not a mu follower as I asserted in the previous post. However the sweet spot can be calculated in a manner similar to the mu follower.
The equations in the previous post appear to be correct and can be used to calculate RL in order to achieve the sweet spot. Furthermore, using a triode model for the SIT gives additional useful equations.
Being able to determine gm[M1E] allows one to choose the value of the degeneration resistor for PFET M1:
Rlo = 1/(1/gme[M1]-1/gm[M1])
DEFiSIT is not a mu follower as I asserted in the previous post. However the sweet spot can be calculated in a manner similar to the mu follower.
The equations in the previous post appear to be correct and can be used to calculate RL in order to achieve the sweet spot. Furthermore, using a triode model for the SIT gives additional useful equations.
Being able to determine gm[M1E] allows one to choose the value of the degeneration resistor for PFET M1:
Rlo = 1/(1/gme[M1]-1/gm[M1])
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Hi Lynn, we are all waiting .....
wait or no wait , my 2 gray cells are already in pain
I have been working on many aspects of the SITs and the mu-follower.
I have measured a total of five 2SK182ES SITs and found the sweet spot behavior to be similar for all of them. I do not have access to any SITs other than the Tokin 2SK182ES to measure, so I do not know about the sweet spot behavior of any other SITs.
I have started bench testing a mu-follower circuit with the optocoupler LED connected to a sense resistor on the MOSFET drain rather than the source as in the SIT-2. See the circuit below. A potential advantage of this circuit is that the degeneration resistor Rhi can be arbitrarily chosen, independent of the idle bias current and the Rmu gain resistor of the mu-follower. If Rhi has zero resistance, then M1 will behave more like an square-law device and have higher effective transconductance (gme). As Rhi is increased, M1 behaves more linearly and have a lower gme, which can be compensated for by increasing the value of Rmu, such that beta=1+Rmu*gme has the desired value. Is it possible to improve the harmonic structure by carefully choosing Rmu and Rhi?
I have measured a total of five 2SK182ES SITs and found the sweet spot behavior to be similar for all of them. I do not have access to any SITs other than the Tokin 2SK182ES to measure, so I do not know about the sweet spot behavior of any other SITs.
I have started bench testing a mu-follower circuit with the optocoupler LED connected to a sense resistor on the MOSFET drain rather than the source as in the SIT-2. See the circuit below. A potential advantage of this circuit is that the degeneration resistor Rhi can be arbitrarily chosen, independent of the idle bias current and the Rmu gain resistor of the mu-follower. If Rhi has zero resistance, then M1 will behave more like an square-law device and have higher effective transconductance (gme). As Rhi is increased, M1 behaves more linearly and have a lower gme, which can be compensated for by increasing the value of Rmu, such that beta=1+Rmu*gme has the desired value. Is it possible to improve the harmonic structure by carefully choosing Rmu and Rhi?
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I believe it is ..... but , again , only up to some extent
as you know , R load ( speaker) is dominating whatever we throw on top of SIT ;
after that , second dominant factor is Uds
so , fully optimized circuit for exact SIT specimen must have adjusted rail , Iq and SIT Uds
which you already did show from start of this thread
as you know , R load ( speaker) is dominating whatever we throw on top of SIT ;
after that , second dominant factor is Uds
so , fully optimized circuit for exact SIT specimen must have adjusted rail , Iq and SIT Uds
which you already did show from start of this thread
My previous posts about the SIT "sweet spot" and the various circuit equations have dealt with the small signal behavior of the SIT and mu follower, at around the 1 Watt power output level.
I am finding it much more difficult to understand the large signal behavior where the circuit is reaching the class A limits and beyond, which requires a good large signal device model for the mu follower NFET, and the SIT.
More to follow.
I am finding it much more difficult to understand the large signal behavior where the circuit is reaching the class A limits and beyond, which requires a good large signal device model for the mu follower NFET, and the SIT.
More to follow.