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Tokin SIT DEFiSIT musings
Tokin SIT DEFiSIT musings
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Old 18th December 2019, 08:52 AM   #21
Zen Mod is offline Zen Mod  Serbia
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Tokin SIT DEFiSIT musings
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Old 18th December 2019, 01:08 PM   #22
woofertester is offline woofertester  United States
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This lash-up is un-degenerated and self-biasing. + / - 33V, ~1.5A 50 deg C.
The tempco of this DEFiSIT pair is only very sightly positive. It does not run away like a naked MOSFET runs away. I believe that this makes the temp stability problem only a matter of how big and/or efficient the heatsink is.

I think I have a feel for how this works. I have ordered some parts to see if I can get the self-biasing rail voltages lower for the same or even higher current.

Just waiting for parts in transit now.

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Old 19th December 2019, 02:14 PM   #23
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Default SIT accelerator

In the BAF 2016 talk by Nelson, he shows a schematic labeled "DEPLETION / ENHANCEMENT FOLLOWER 2"

That schematic sets the bias of the SIT more negative than the bias of the enhancement MOSFET.

I call this putting the brakes on the SIT.

What my pair of devices requires is applying the accelerator to the SIT.

A re-drawn schematic of my pair of devices is attached. The Vgs values are for power supplies of + / - 24V at Ids = 1.65A at 48 deg C with zero offset between output and power supplies common.
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File Type: jpg DEF_accelerator.jpg (22.9 KB, 407 views)

Last edited by woofertester; 19th December 2019 at 02:17 PM.
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Old 19th December 2019, 06:14 PM   #24
claudio52 is offline claudio52  Italy
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Tokin SIT DEFiSIT musings
Hi woofertester, take a look at post #108/DEF Amp. I think function 3 also adapts to Vgs of the PMos more negative of NJ.
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Old 19th December 2019, 08:44 PM   #25
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Hi woofertester, take a look at post #108/DEF Amp. I think function 3 also adapts to Vgs of the PMos more negative of NJ.
It looks to me that his SIT gate was more negative than his PMOS gate in all of the schematics on that page.
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Old 20th December 2019, 02:55 PM   #26
claudio52 is offline claudio52  Italy
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Yes, it's true, I wanted to say that yours too string resistances with Vgs PMos > Vgs NJ, in absolute value, adjusts the output offset.
This is may last DEF experiment. There is the most negative FET enhancements mode. Before reaching a stable offset, Vos went up and then back down. DEF Ultimo schema-jpg 2.jpg
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Old 20th December 2019, 07:13 PM   #27
woofertester is offline woofertester  United States
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I find that the output stage when cold has 150 mV of offset. The output stage is set for 0v offset at 50 deg C.

The offset is definitely dependent on temperature

My guess is that a resistor array with one or more thermistors can reduce the drift of offset over temperature.

A very gentle DC servo may be worth investigating.

My initial desire is to use this as a DC coupled follower much like an F4.

For the pair of devices that I am using, 67 mV is the difference between the two gate voltages.
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Old 20th December 2019, 07:36 PM   #28
Zen Mod is offline Zen Mod  Serbia
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I care about DC offset when in temp equilibrium

while arriving there , I don't care even for 1V5 , it'll not harm even hysterical Lowthers and such , under sole condition that nothing is abrupt
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Old 20th December 2019, 07:42 PM   #29
woofertester is offline woofertester  United States
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Quote:
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I care about DC offset when in temp equilibrium

while arriving there , I don't care even for 1V5 , it'll not harm even hysterical Lowthers and such , under sole condition that nothing is abrupt
Good to know. I will not worry about it then.

If laying out a PCB, it should be simple to have a network and and a couple of jumpers that will handle the cases of SIT Vgs being either low or higher than P-FET Vgs.
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Old 21st December 2019, 08:46 AM   #30
claudio52 is offline claudio52  Italy
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Thank you Zen Mod. An all the more reason to continue the studying the DEF Amp.
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