Buffer with Dual N-Ch Jfets and Dual Power Supply

Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.
Assume that you have shorted the input gate to Gnd, and your rail voltages are symmetrical to say 0.1V.
Then something is likely to be wrong with your matching.

If you have matched to 10µA under the same temperature, I expect your offset to be < 1mV.
That is when you use Fig. 15c with Rs = 0.


Patrick
 
Member
Joined 2000
Paid Member
After 4 hours, and turning on the DMM, still settles at .9mA. Goes from 1.1mA down to .9 after a few seconds.

I'm using an 18 Ohm source resistor, because that's close to what the article use and thought it would be safe since I'm using 15v+/- source. I'm having trouble calculating the Rs value.
 
Member
Joined 2000
Paid Member
One more question. I'm not trying to state the obvious here, but not sure of the impact of needing matched quads.

For example, I have a well matched pair of sk170s at 9.76mA for channel 1 and another set at 10.50 and 10.52mA for channel 2.
Will there be, let's call it, a "balance" issue between channels?
I want to assume- Yes they should be quad matched, because they are technically biased at different currents,
but if that's what they require to be at 90% of their Idss, then does it matter if both channels have quad matched JFETs?

Thanks,

Vince
 
Last edited:
Status
This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.