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Old 26th September 2018, 08:35 PM   #21
Pascal Nguyen is offline Pascal Nguyen  Australia
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Default Erratas

Quote:
Originally Posted by Zen Mod View Post
yup

mistake with grounds in drawing

3 most left ones , need to go to neg. supply
Hi ZM,
Long time no see

Double check, Spot one error:

B1 supply got to be higher than 24v to provide -17.8v for SIT gate.
This value needs to be adjusted for different SIT

Cheers
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Old 26th September 2018, 09:28 PM   #22
juanitox is offline juanitox  France
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Quote:
Originally Posted by Pascal Nguyen View Post
If I can so do you
you don't know me yet

one exemple of my dumbiness : this amp must need some gain so do you think a simple single ended gain circuit with N channel Vfet 2SJ74 with -17V VDS direct coupled to the gate of the second stage would work ?
so we will need only one negative supply for the amp ?
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Last edited by juanitox; 26th September 2018 at 09:38 PM.
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Old 27th September 2018, 01:09 AM   #23
Chul is offline Chul  South Korea
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Quote:
Originally Posted by Pascal Nguyen View Post

Pink candle, haha, poor man lubricants for threading and bicycle chain.
That's what I thought. I would like to try myself!
It can be better than spilling the tapping oil.
I also remember that our old generation used the candle for sliding drawers.

I look forward to your progress with the circuit.
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Old 27th September 2018, 08:53 AM   #24
Pascal Nguyen is offline Pascal Nguyen  Australia
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Quote:
Originally Posted by juanitox View Post

...a simple single ended gain circuit with N channel Vfet 2SJ74 with -17V VDS direct coupled to the gate of the second stage would work ?
so we will need only one negative supply for the amp ?

It should be P channel, you meant,
Sure it does work as a voltage amplifier for driving the pair SIT - Lateral buffer by providing a nťgatif 17.5v (this value was measured from my prototype).

But how well it is, i donít know, havenít got any P 2SJ74 fet at hand, only made a comment by looking at the 2SJ74 spec.
At 17.5 Vds, you have very little chance to create any H2 with negative phase.


Salut
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Old 29th September 2018, 11:08 AM   #25
juanitox is offline juanitox  France
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Click the image to open in full size.

first stage the transistors are finally here.
to see if it can works i presume that i must check if at the Same VDS et IDS i'v got he same VGs on the quad chips ; is there a safe margin or it must be perfectly matched ?
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Old 29th September 2018, 01:33 PM   #26
avtech23 is offline avtech23  Australia
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Quote:
Originally Posted by Pascal Nguyen View Post
Without Mr Pass and many contributors to the Pass Labs Forum, I wouldnít have a clue what is concerning a class A SIT audio amplifier.
Those information helped me to build an SIT amp with a complementary lateral mosfet, my LATE - SIT
Nice work, Pascal!
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Old 29th September 2018, 04:48 PM   #27
Pascal Nguyen is offline Pascal Nguyen  Australia
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Quote:
Originally Posted by juanitox View Post
first stage the transistors are finally here.
to see if it can works i presume that i must check if at the Same VDS et IDS i'v got he same VGs on the quad chips ; is there a safe margin or it must be perfectly matched ?
Step one:

Thermal test
Mount 4 beefy but cheapest mosfets to heatsink, the one intended for your project.
Connect drain-source to your power supply (30V/5A)
Connect gate-source to a variable 0-9v, adjust to 4A Ids
Heatsink must be within 50 degC at room ambianceís 22degC

Step two:

Mount 2 Sits and 2 Laterals to heatsink. (Precaution anti static, grounded soldering iron tip, temporarily shorted Sit gate-source).

Connect BUZ905D Drain-Source to 15V3A power supply
Adjust Gate-Source with 0-9V variable to reach 2A.
Lock and record the value of Vgs@2A

Connect BUZ905D and THF-51S according to the schťma.
Connect +30 to chassis and -30 to BUZís drain.
Connect BUZís gate-source to the locked variable 0-9V supply.
Connect Sití gat-source with a second variable 0-9V supply and adjust it until both transistors have an equal 15V Drain-Source.
Record that value.

Repeat for all transistors, to get all value Vgs, donít have to match 100%, as close as you can get for left and right channels

Using correct amperage and colour coded electrical wire with idiot proof polarity connectors.

Donít forget a Dubonnet for calming down your nerves

Cheers
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Old 29th September 2018, 04:49 PM   #28
Pascal Nguyen is offline Pascal Nguyen  Australia
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Quote:
Originally Posted by avtech23 View Post
Nice work, Pascal!
Thanks for your encouragement

Cheers Mate
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Old 29th September 2018, 05:09 PM   #29
Pascal Nguyen is offline Pascal Nguyen  Australia
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Default V2

V1 had been poorly designed for biasing the output transistors.

I used the trimpot of the DN2540 current regulator to change Vbias, that did affected the linearity of the driver due to current variation.

The V2 has separated V bias adjustment, no interference with Driver current that would move the DN2540 out of the square law corridor (70mA / 10Vds)

How does it works:

Upper DN2540 supplies 70mA as CCS to the lower DNís with 22 Ohm source resistor.
That resistor will potentially different the gate by 1.5V, where the DN is behaving just like a triode but the output generates only positive H2

The Driver will bias and reverse its output to the power stage then assuming a voltage conversion to current will happen with a taste of H2 negative.



Cheers
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Old 29th September 2018, 05:38 PM   #30
juanitox is offline juanitox  France
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hi , pascal thanks for the test procedure. something i don't understand ( again ) in the V2 schematic how the VFET and mosfet negative bias could be done with 32V positive supply ?
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