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Old 18th January 2019, 10:15 AM   #541
Ian Macmillan is offline Ian Macmillan
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You say that the lower OLG versions did not make any improvement but did they actually sound different to the high OLG version? Or maybe they sounded worse?
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Old 18th January 2019, 12:45 PM   #542
generg is offline generg  Germany
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I can say at the moment that using around 18R as drain resistors for the J-fets in the input stage (around 45dB OLG) sounds very different and for my ears much better than the version with 70dB OLG.
When I used like Lynn some time ago a 1k load, I had not such a good impression.
But sound comparing in memory is fairly nonsense.

Of course the first nights with a new build are mostly the most exciting..... :--))

The sound is much more sweet, and airy. Maybe a bit too soft, I must try a bit higher values maybe up to 100R.

And Ian, I see no danger for the J-Fets or unusual hard work when I compare the situation to their place in F4 or F6. Here we have source resistors with about 10R and rails with +/-23V, don't they have a harder life here?

In my build they see only +/-12V because of cascoding.
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Old 18th January 2019, 12:51 PM   #543
Ian Macmillan is offline Ian Macmillan
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Interesting. Perhaps some of the sound difference may be down to the different damping factors.

When I said "work hard", I meant that driving a lower load means more current variation through the JFETs for a given signal level which typically results in more distortion. I didn't mean to imply that you were exceeding their rating or anything like that.
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Old 18th January 2019, 12:54 PM   #544
generg is offline generg  Germany
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Ah, now I understand better... thanks!
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Old 18th January 2019, 04:58 PM   #545
lhquam is offline lhquam  United States
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Quote:
Originally Posted by Ian Macmillan View Post
Interesting. Perhaps some of the sound difference may be down to the different damping factors.

When I said "work hard", I meant that driving a lower load means more current variation through the JFETs for a given signal level which typically results in more distortion. I didn't mean to imply that you were exceeding their rating or anything like that.

It might be easier to understand the signal levels by working backwards from the amplifier output. For the XA25, the two voltage gain stages are the JFETs (K170/J74) and the VAS (K2013/J313), ignoring the relatively small voltage attenuation from the output stage. For a given output level Vout, the input to the VAS must be Vout/A(VAS), where A(VAS) is the voltage gain of the VAS. Thus, the necessary voltage input to the VAS is unaffected by changing the JFET load resistors, but, as Ian said, the JFET currents are increased. Similarly, if the gain of the VAS is changed by lowering the load resistance on the VAS output, then the required input to the VAS must be increased, thus increasing the JFET currents.


What magnitudes are involved here? With VAS stage gain of 80dB (assuming a 33K load on the VAS output) and an output voltage of 4V Peak (1Watt into 8R), the input to the VAS must be 400uV peak. With 100R JFET drain load resistors the AC current must be 4uA peak. With 10R JFET drain load resistors the AC current must be 40uA peak. Are either of those AC currents large enough to cause significant distortion from the JFETs?
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Old 18th January 2019, 05:08 PM   #546
Ian Macmillan is offline Ian Macmillan
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You wouldn't think that such low values of current variation would have much impact but then these are only at 1W output. However, I made my comments based on the distortion figures shown by simulations with varying resistances and the changes appear very real though I should perhaps add the caveat that we are talking fairly low levels of distortion anyway. All counts though if we are aiming at figures like .00x%
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Old 18th January 2019, 05:10 PM   #547
generg is offline generg  Germany
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Quote:
Originally Posted by lhquam View Post
It might be easier to understand the signal levels by working backwards from the amplifier output. For the XA25, the two voltage gain stages are the JFETs (K170/J74) and the VAS (K2013/J313), ignoring the relatively small voltage attenuation from the output stage. For a given output level Vout, the input to the VAS must be Vout/A(VAS), where A(VAS) is the voltage gain of the VAS. Thus, the necessary voltage input to the VAS is unaffected by changing the JFET load resistors, but, as Ian said, the JFET currents are increased. Similarly, if the gain of the VAS is changed by lowering the load resistance on the VAS output, then the required input to the VAS must be increased, thus increasing the JFET currents.


What magnitudes are involved here? With VAS stage gain of 80dB (assuming a 33K load on the VAS output) and an output voltage of 4V Peak (1Watt into 8R), the input to the VAS must be 400uV peak. With 100R JFET drain load resistors the AC current must be 4uA peak. With 10R JFET drain load resistors the AC current must be 40uA peak. Are either of those AC currents large enough to cause significant distortion from the JFETs?
Now I understand still more better!

Thanks thanks!

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Old 18th January 2019, 05:12 PM   #548
lhquam is offline lhquam  United States
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When you get to extremely low distortion levels, LTSpice double-float calculations could become problematic. Off hand, I do not know the LTSpice noise-floor. It might not be an issue for THD>0.0001%.
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Old 19th January 2019, 05:04 AM   #549
lhquam is offline lhquam  United States
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Here is another avenue to explore. Put feedback around the FE only, thus loading the FE with the bias neterok and the feedback network. The output damping factor will become low, determined only by the transconductances of the output FETs. And the harmonics will be mostly defined by the OS, since the FE will have very low distortion.
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Old 19th January 2019, 08:42 PM   #550
PKI is offline PKI  United States
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...The output damping factor will become low...
why would we want that?!
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