THe argument seems to be over the contribution of the two fets and whether or not they are equal. If they are indeed, not equal, then you have as some have suggested, another JLH on your hands because you have lost your symmetry due to the response of the fets. I am probably wrong, but if using true complimentary pairs, the symmetry is maintaned all the way through to the Load. The only way it is truly symmetrical with a N channel fet is if both fets are doing exactly the smae thing at the same time, correct.
Maybe a collaboration by kasey197, ilhquam, and flg. The first two built a prototype, and all three simulated Conceptual F6. ZM maybe the referee and/or the leader of this group.no way , Bubba
I'm too much of hysteric guy , to be able to summarize
There is valuable [and redundant] R&D information which is scattered all over the 1000 posts. A concise summary will give DIYers a fresh focus to move forward effectively towards the target.
Buzz, they're equal mate. The only other topology that has the same degree of symmetry is the circlotron..... IMHO of course 
Theory, inspection and experimentation all arrive at the same point. I found that unlearning what I (thought) I understood was pretty hard. It's easier for some. And harder for others.
Theory, inspection and experimentation all arrive at the same point. I found that unlearning what I (thought) I understood was pretty hard. It's easier for some. And harder for others.
That's cool ! One month, a thousand posts ... on a concept ! Gives you an sense about the power and attraction of this design.... It's interesting how simple the idea is in principle, but how much harder it turns out to put into practice!
kasey197: You are in a position to jot down several [undisputed] bullet points regarding the design and operation of Conceptual F6. For example the simple ones I know todate are:
- The signal drives of the transformer's secondary are equal in amplitude and out of phase with each other[ i.e. matched per Pass]
- The output JFETs are matched [per Pass]
- The idle bias of the upper JFET is referenced to the output [or not; your point of view?].
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Ah ..., there is nothing undisputed so far about this design matey
) just undisputed in my own head !! Am building the danged input buffers tonight (finally) so will post something unless one of he kids wakes up with a nightmare first !!!Bonne nuit.Ah ..., there is nothing undisputed so far about this design matey
Actually, the circlotron is truly symmetric whereas the F6 (and quasi-complementary designs in general) has asymmetries due to the transformer parasitic capacitances.Buzz, they're equal mate. The only other topology that has the same degree of symmetry is the circlotron..... IMHO of course
Theory, inspection and experimentation all arrive at the same point. I found that unlearning what I (thought) I understood was pretty hard. It's easier for some. And harder for others.
1 MOSFET does not output a semetrical sinewave at the input!
2 MOSFETs of the same type "may" have a curve sufficient to find an operating point where, the non lineararities(unsemetrical performance)(distorion) of one, is mirrored by the other, in which case the nonlinearities cancel. But, have you won the lottery lately?
Otherwise, I agree, the Circlotron has the best oportunity to be such a balanced, symetrical, linear design.
I'm not building an F6 after I'm done with my F4 & 5, I'm building a SiClotron
CAPACITOR WARNING
I hate capacitors.
I have been experimenting with "tweaks" in my bias circuit in an attempt to lower THD at low frequencies and discovered that it is possible to provoke oscillation at .2-.3Hz, depending on the RC time constants related to the capacitors. Looking at the LTSpice AC analysis plots, there is a peak in the response at these frequencies and very bad phase margin.
I need to crack open the books and learn how to solve this problem.
I hate capacitors.
I have been experimenting with "tweaks" in my bias circuit in an attempt to lower THD at low frequencies and discovered that it is possible to provoke oscillation at .2-.3Hz, depending on the RC time constants related to the capacitors. Looking at the LTSpice AC analysis plots, there is a peak in the response at these frequencies and very bad phase margin.
I need to crack open the books and learn how to solve this problem.