Enhancement mode JFET

[808eengr]

there is a difference between the N and P types.
not so easy to fab.


1+1+4 year patent license is up pham.


sing ya later! ( .68 B euros later to the bank ;] )

 

[808eengr]

YouTube


YouTube

 

[808eengr]

heard those supposedly linear transfer jfets are referred to as 'blobs' in the industry. guess the process yields what looks like 'blobs' on die, thus the moniker.

 

[scott wurcer]

there is a difference between the N and P types.
not so easy to fab.

There is no such thing as an enhancement mode JFET. There is no way to create a built in field to adjust the threshold like a MOSFET.

EDIT - It must be happy hour.

 

[808eengr]

the solar inverter revolution + efficient inverter A/C units


do those use transistors??


:shrugs:

 

[808eengr]

There is no such thing as an enhancement mode JFET. There is no way to create a built in field to adjust the threshold like a MOSFET.

of course not.


because you said so.

 

[808eengr]

in the end, climate change was reduced. that's a plus

 

[808eengr]

There is no such thing as an enhancement mode JFET. There is no way to create a built in field to adjust the threshold like a MOSFET.

EDIT - It must be happy hour.

YouTube

 

[808eengr]

YouTube


EDIT: @home working


search_query=Me, Myself, and I

 

[808eengr]

we'll just write you off by that much


good talk

 

[scott wurcer]

of course not.


because you said so.

Sorry physics says so.

 

[PRR]

...........the process yields what looks like 'blobs' on die,............

There is no such thing as an enhancement mode JFET. There is no way to create a built in field to adjust the threshold like a MOSFET.
EDIT - It must be happy hour.

"Blob" may imply they are hiding something. A teeny battery?

It seems to be happy WEEK. Cheers!

 

[MarcelvdG]

How would you call a Semelab SML100M12MSF then?

SML100M12MSF Semelab / TT Electronics | Mouser Europe

 

[syn08]

Sorry physics says so.

True for the standard JFET device.

Not true for non standard and a hardly integrable layout and process:

US7180105B2 - Normally off JFET
- Google Patents

 

[syn08]

How would you call a Semelab SML100M12MSF then?

SML100M12MSF Semelab / TT Electronics | Mouser Europe

Much easier to do on wide bandgap materials like SiC, since they allow forward biasing the JFET gate without much leakage. A heroic effort is required for a normally off silicon JFET, see the above Infineon patent. The “pinch” voltage in this case is limited to some 0.2-0.4V before the exponential gate current kicks in and makes a mess of the conduction mechanism. Under the circumstances, I would think a high channel conductance would require a huge silicon area.

 

[808eengr]

"Blob" may imply they are hiding something. A teeny battery?

It seems to be happy WEEK. Cheers!

Regards

thanks for the advice on transistors way back

 

[808eengr]

Sorry physics says so.

what is this physics you speak of??


here's the small signal

 

[808eengr]

Sorry physics says so.

what is this physics you speak of??


revisited

 

[808eengr]

now how in the world could two devices be placed on the same epitaxial layer?





just put them on the die precisely, like an older chipset for a XEON perhaps


pennies on the dollar for the full process lolol

 

[808eengr]

LMGTFY