A reverse-biased diode across the base-emitter junction will add a small capacitance and a bit of leakage current, but both should be negligible as long as it is a small silicon junction diode, 1N4148 or so.
In the current configuration the second stage transistors do not achieve good common mode noise. A standard LTP with a common emitter resistor is effectively noise cancelling. The circuit does not have a viable DC operating point.
A quick adjustment. Reduce the emitter resistors of the first stage to 4.7k. Move the gain adjustment scheme to the second stage. As long as the DC voltages are balanced the transformers won't complain. Also if there is good DC balance the cap can be removed. The noise will drop as the gain increases because the noise becomes common mode. At min gain there may be some HF peaking or instability but this can be dealt with later.
A quick adjustment. Reduce the emitter resistors of the first stage to 4.7k. Move the gain adjustment scheme to the second stage. As long as the DC voltages are balanced the transformers won't complain. Also if there is good DC balance the cap can be removed. The noise will drop as the gain increases because the noise becomes common mode. At min gain there may be some HF peaking or instability but this can be dealt with later.
Okay now I'm seeing it. With the first stage using PNP transistors I was thinking about it backwards.
I'm not quite as worried about the CMRR of the circuit given that it has a transformer input- that's part of why I like transformer balancing. That said, I can play around with an LTP in the simulation and see how it behaves.
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H713, have you looked at DC conditions ?
With 10Ks you have near zero VCE at the transistors, that is way too low, they are too close to saturation. Usually there should be 5V or more VCE.
For the second stage, you can use a LTP configuration, it makes little difference if any from the 3 resistors set as you have in the original schematic.
With 10Ks you have near zero VCE at the transistors, that is way too low, they are too close to saturation. Usually there should be 5V or more VCE.
For the second stage, you can use a LTP configuration, it makes little difference if any from the 3 resistors set as you have in the original schematic.
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VCE was about 1 volt. I changed some resistor values around a bit to get around 5v VCE. Distortion dropped slightly as well, down from .001% to about .0008%. I'll post an updated schematic tonight.
Alright, here's my latest version of the schematic. In addition to changing a few resistor values, I put in the diodes as suggested. I also came to my senses and realized that the chances of me getting perfectly matched transistors was basically nil, so I decided to AC couple to the transformer to avoid saturating the core.
Alright, here's my latest version of the schematic. In addition to changing a few resistor values, I put in the diodes as suggested. I also came to my senses and realized that the chances of me getting perfectly matched transistors was basically nil, so I decided to AC couple to the transformer to avoid saturating the core.
A typo: D1, D2 are shorted. You do need D1 and D2 to protect against a phantom power fault ( When a short happen at the mike cable with phantom power on. This should not happen.....but it does...). I do not think phantom faults can reach to damage the second stage, so D3,D4 are not necessary. What others think ?
What gain and distortion do you get with feedback and without feeback ?
I am not familiar with these transformers to know about core saturation from transistor mismatch, I have no idea what DC is acceptable saturation wise.
What gain and distortion do you get with feedback and without feeback ?
I am not familiar with these transformers to know about core saturation from transistor mismatch, I have no idea what DC is acceptable saturation wise.
I think that without the diodes in the second stage, it is hard to guarantee that the reverse base-emitter voltages of the second stage transistors will always be less than 5 V. I also think the extra diodes don't do much harm. So I would just include the diodes in the second stage.
Jensen explicitly warns against measuring signal transformers with a multimeter set to measure resistance, because the remanent magnetization would cause an increase in second-order distortion. That is, the test current of a typical multimeter is too high to be acceptable. I don't think they specify anything more specific than that.
Jensen explicitly warns against measuring signal transformers with a multimeter set to measure resistance, because the remanent magnetization would cause an increase in second-order distortion. That is, the test current of a typical multimeter is too high to be acceptable. I don't think they specify anything more specific than that.
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An attempt to guess estimate a DC voltage acceptable at the output transformer.... Assuming this transformer is designed for line level. Assuming line level saturates at +10dBu, that is 3.5V peak My guess is that a DC 10% of this doesn't change much about the transformer core saturation. My gess is 350mV DC would be acceptable. This is a wild wild guess, just to have some idea.
Now, what about the DC we can have at the output of this circuit. It all depends of the matching of the transistor. Blindly using simulation will show, none... DC offset depends of the match in Hfe and Vbe of the transistor pairs, and the feedback helps reducing DC offset. Vbe mismatch doesn't matter at the first stage, because of the capacitor. Hfe mismastch at the first stage does matter. Hfe and Vbe mismatch at the second stage matters. It would be interesting to calculate the expected DC offset with for example 5% Hfe mismatch and 1mV Vbe mismatch. The simulator can be used for this calculation using transistor models modified accordingly, BR is the Spice transistor model pararameter for Hfe, while IS is the parameter that changes Vbe.
Now, what about the DC we can have at the output of this circuit. It all depends of the matching of the transistor. Blindly using simulation will show, none... DC offset depends of the match in Hfe and Vbe of the transistor pairs, and the feedback helps reducing DC offset. Vbe mismatch doesn't matter at the first stage, because of the capacitor. Hfe mismastch at the first stage does matter. Hfe and Vbe mismatch at the second stage matters. It would be interesting to calculate the expected DC offset with for example 5% Hfe mismatch and 1mV Vbe mismatch. The simulator can be used for this calculation using transistor models modified accordingly, BR is the Spice transistor model pararameter for Hfe, while IS is the parameter that changes Vbe.
All 4 diodes are staying in. I can always not populate them into the PCB if I choose, but I know that if I leave them out of the layout it's going to bite me in the tail later on.
I also decided to AC couple to the transformer. Even if I got all perfectly matched transistors, I still have to take into account temperature changes and drift over time. Also, bearing in mind that I may be building up to 26 of these if I like them enough to put them in my console, then a minor transistor mismatch only results in higher distortion, rather than saturating the core of the transformer. This also means that the preamps will likely be more consistent from one to another.
Also, I'm reading between .0007% and .002% THD in LTspice depending on how hot the input signal is. Of course, that doesn't mean it will be any good, after all plenty of the best studio mic pres aren't exactly low distortion, but it's somewhere to start. I do hope that using discrete transistors for most of it will make it a little less boring than an entirely op-amp based design.
Quite honestly, I haven't seen any microphone preamps using balanced circuitry all the way through, so I'm interested to see how it performs.
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My favorite are these: _Monte Generoso from Samuel Groner Analog Circuit Design · Samuel Groner · Resources · Microphone Preamplifiers _Double balanced...from Graeme Cohen http://leonaudio.biz/double.balanced.mic.amp.notes.pdf Here is documented how they perform. About THDs from simulations, you are right. Transistor models are not accurate. Simulation with identical transistors perfectly cancel all even harmonics. I use simulation to calculate rather than expecting to see realities.
Agreed- Simulations are good for a ball-park estimate on performance. If it simulates .0001% THD, then it's probably (but not necessarily) going to have good THD performance in reality.
In addition, I decided to see what would happen if I ditched the op-amps all together and replaced them with emitter followers. I was pleasantly surprised that it performed close to as well as the op-amps. I then changed the connection for the negative feedback to the output of the emitter followers, and then reconfigured a few resistor values to get the THD even lower. Attached is what I came up with. Performance lookes good, THD was only about .001% putting out 4V peak into a 600 ohm load. I will wait until I breadboard it to see if I need to do anything to keep those emitter followers from oscillating.
In addition, I decided to see what would happen if I ditched the op-amps all together and replaced them with emitter followers. I was pleasantly surprised that it performed close to as well as the op-amps. I then changed the connection for the negative feedback to the output of the emitter followers, and then reconfigured a few resistor values to get the THD even lower. Attached is what I came up with. Performance lookes good, THD was only about .001% putting out 4V peak into a 600 ohm load. I will wait until I breadboard it to see if I need to do anything to keep those emitter followers from oscillating.
Those values seem rather optimistic to me. Besides, it's BF for hFE, the parameter BR sets the reverse current gain (that is, with collector and emitter swapped) and also affects the saturation voltage.
One thing to bear in mind is that this circuit is meta-stable from a DC standpoint. In other words the DC balance can step instead of going through a smooth transition. When the circuit is prototyped, I recommend using a 20K variable resistor for the emitter resistor of the LTP. This can be adjusted so that best balance of headroom and distortion is achieved.
The LTP in the second stage now means that noise is more or less common mode. This gives a good degree of tolerance for selection of transistors. The optimum noise performance is dependent on collector current. There are probably better transistors for the operating currents here.
The LTP in the second stage now means that noise is more or less common mode. This gives a good degree of tolerance for selection of transistors. The optimum noise performance is dependent on collector current. There are probably better transistors for the operating currents here.
Yes, BF ( typing mistake ).
Optimistic values as a starting point. ( These are what I use in my simulation, assuming matched pairs )
Only one cap is needed at the output. With one cap the drawing does not look balanced but the circuit behavior stays balanced.
I do not think so. That could be the case with positive feedback.
This version has good DC stability. However the gain seems to be too low. So I was playing with a different version and forgot it wasn't the original config.
What is the expected max gain of the circuit? I am not seeing what I would normally expect.
Ignore last post. Picked up a bug re-drawing the last rev. Everything seems fine. In fact excess gain may be an issue. A small resistor in series with the pot might be needed. See what noise sims like with 2N4403 as the first pair.
What is the expected max gain of the circuit? I am not seeing what I would normally expect.
Ignore last post. Picked up a bug re-drawing the last rev. Everything seems fine. In fact excess gain may be an issue. A small resistor in series with the pot might be needed. See what noise sims like with 2N4403 as the first pair.
Accurately ?
Indeed, RE is a parameter of Spice bipolar models.
RE default value is 0. For a few bjt models I looked at, there is no RE or a very small like RE = 0.1
This is why I prefer to use re = KT/qIc