RD30 – Quad multibit d/a converter

[regal]

Originally Posted by Lupulroz

There are 2 main clocks involved, and both are external XO's. One is a high-frequency clock involved in sampling the input signal; second - and key of the reclocking system, combined with fpga internal ram buffer - is the Si570 DCO. This allows the creation of a PLL entirely in the digital domain (all-digital-pll). The performance of the ADPLL is essentially given by the performance of the Si570, which offers a remarkably low phase noise for a DCO.
The Bytemorph DF is actually a collection of 3 independent filters; they are indeed integers (no ASRC). There is a 8x filter for 44.1k and 48k; a 4x filter for 88.2 or 96k input; and a 2x filter for 176 and 192k. The filters are switched on-the-fly when sample rate changes. I will come back with detailed DF performance in the next posts.

This is an awesome project. The concept reminds me of a modern version of some of the best DAC's of years past.

What is the low end cut-off frequency of the PLL ?

Also the idea of multiple digital filters is great especially with the USB port.


How are you handling the ground with the FPGA being such high speed, is there possibility of it interferring with the PCM ?

[Lupulroz]

Originally Posted by regal

This is an awesome project. The concept reminds me of a modern version of some of the best DAC's of years past.

What is the low end cut-off frequency of the PLL ?

Also the idea of multiple digital filters is great especially with the USB port.

How are you handling the ground with the FPGA being such high speed, is there possibility of it interferring with the PCM ?

Hi regal,
the low-end cut-off frequency of the PLL is 0.5 Hz.
There are separate ground planes for FPGA and PCM - and we did not found interferences.
Yes, the idea was to have a high-performance design without the use of an ASRC. We are using fully the 38 bit frequency resolution of SI570 - to achieve that is was quite a challenge.

[Lupulroz]

Originally Posted by bear

Looking forward to seeing that...

Top layer layout for RD30.

[Lupulroz]

RD30 FFT plots, 1Khz and 10KHz respectively, -20 dBFS signal.

[regal]

I really like this, do you have plans for an apodizing filter ?

[Lupulroz]

Originally Posted by regal

I really like this, do you have plans for an apodizing filter ?

I already have an apodizing filter available. I can supply the dac with it, instead of linear phase. Another option - which sound best of all to my ears - is a convolution FFT type, which is impulse response optimized - somewhat a combination between minimum phase and linear.

[Telstar]

Very good job, my compliments.

How is the clock handled between the usb DDC and the i2s at the DSP?
The main issue i see with the current interfaces is that they are not slaved to the DAC master clock (which should be as close as possible to the converters).

Thanks in advance for your reply.

[regal]

Originally Posted by Telstar

Very good job, my compliments.

How is the clock handled between the usb DDC and the i2s at the DSP?
The main issue i see with the current interfaces is that they are not slaved to the DAC master clock (which should be as close as possible to the converters).

Thanks in advance for your reply.

This is a PLL design, not a DAC master - Transport slave. Is your concern the lack of reclocking after the DSP? It doesn't make since with a PLL. You might want to read the tent labs DAC topology : 1. Jitter suppression and PLL design

See Figure 5, with this RD30 the PLL is intergrated with the DSP.

From my perspective this is a modern version of that classic design, similar also to the Pass D1's method of dealing with jitter.

I like this approach, if the code is good this will work to give very good jitter performance.

But to be honest I sort of like the iancanda fifo buffer approach better just because the code has to be right, in other words if the code is wrong it just won't play (skips).

With the RD50 the way to prove it is working as intended is measurement, which is fine I trust the designers work.

Either approach is way up there with +$10k commercial DAC's.

[Telstar]

Any PLL has intrinsic jitter. I would have preferred the usb slaved to the DAC, but I reckon this approach is more flexible and it works for the other inputs (where otherwise a clock signal would have been required).

Did you see the jitter measurements?

[Lupulroz]

Originally Posted by Telstar

Any PLL has intrinsic jitter. I would have preferred the usb slaved to the DAC, but I reckon this approach is more flexible and it works for the other inputs (where otherwise a clock signal would have been required).

Did you see the jitter measurements?

I guess the term "PLL" induced some misunderstanding. The USB is actually slaved to the dac; when usb is active the Si570 is programmed with a fixed frequency (22.579 or 24.576 Mhz) depending on the signal sample rate; being asynchronous, all transfers are made after this clock, which is as good as a fixed oscillator.