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Current drive headphone amp in the works
Current drive headphone amp in the works
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Old 10th November 2021, 11:36 PM   #21
abstract is offline abstract  Poland
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I'm not too worried about EQ at the moment -- otherwise I'd never get it finished. I'm keeping my fingers crossed that they will be less sibilant.

New 10V virtual ground.

A lopsided 4:1 emitter resistor ratio seems to improve distortion a bit, probably because the control is also a bit lopsided.
Bias set to about 1.5mA (1k + POT4 = 2.2k).
1V sine through 125 ohms produced a +/-1.4uV sine offset with only 0.4% THD (referenced to H1 = 1.4uV).
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Old 11th November 2021, 05:39 AM   #22
PRR is offline PRR  United States
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Current drive headphone amp in the works
> lopsided 4:1 emitter resistor ratio seems to improve

Because R61 POT4 are reducing the drive to Q12. Bypass cap? Diode bias? It really is another "output stage". (And really does double your losses.)
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Old 11th November 2021, 07:10 AM   #23
abstract is offline abstract  Poland
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At 1.4uV total including the fundamental vs 1,000,000uV signal level, I don't think it matters.

The simulator used a NE5534 model which might have slightly higher gain than the NE5532 that I actually want to use, but it's still nice and slow. I haven't checked the PSRR, but the 20V rail is already regulated.

I may change the pot to 2 parallel thin film resistors.
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Old 24th November 2021, 12:29 PM   #24
abstract is offline abstract  Poland
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The prototype PCB is now in production. Can't wait!

Too many cool things on it for something not to go wrong in the beginning, but we shall see.

I might re-purpose my post/s on the first page to add updates to keep things organised.

Recapping:

Topology:
Single Ended class-A.
First stage: open drain JFET with resistor pull-up and low-pass filtering of the +ve power supply rail.
2nd stage: open drain MOSFET with a 2-stage JFET+PNP constant current source. A 2-stage CCS seemed to give the best of both worlds with the JFET having good distortion matching and the superior ripple rejection of the PNP.

DC coupled:
Instead of a 470u-1000uF output capacitor, together with its self-defeating leakage current and DC offset, the design uses a virtual ground at around 10-12V (adjustable). Maximum simplicity with an NE5532 op-amp boosted with a push-pull PNP-NPN output stage. 1uV ripple vs 1V signal level should be inaudible.

Servo:
A subsonic filtered feedback amplifier (servo) compares the audio output against the virtual ground, and provides local feedback to the MOSFET. Apart from the servo, which has very low gain at audio frequencies, the design relies entirely on emitter degeneration.

It seems to have a lot of stuff for something that is basically:

INPUT-->capacitor-->JFET-->capacitor-->MOSFET --> headphone --> v.ground.


PSU
SMPS with 5V to 24V boost.
Instead of developing a dual PSU, where I would have to consider ripple on both rails, everything is ground referenced.


Anti-thump circuit:

An LPC804 microprocessor monitors voltage levels with resistor dividers and triggers a dual-coil relay. I specifically wanted to avoid wasting power with a "normally off" relay. And the logistics hot-unplugging is still a bit up in the air, but I don't want to do everything at once. The coils can be fired manually so I can start listening while still writing the firmware.
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