This is not a beginner’s project, as we always maintained.
We’ll see how much we can help; But we cannot spoon feed, and certainly not remote debug.
Having said that, a Beta 22 is not much simpler either.
But if you have no understanding of circuitry, then maybe you should not attempt any of our projects.
All NPN & PNP transistors should be matched, including SOT23s and TO220s.
You can do that with a decent DMM which has an hfe-measurement function.
You need min. 50 pcs each for the Toshiba’s, and 20 each for the Sanken’s.
The left-overs from the amp are then used for regulators.
And you will need to have a SOT 23 test socket.
I personally match everything else, including all resistors and caps.
You should at least use 0.5% resistors all over.
Power resistors are best matched using a constant current source of 150mA (made up using a LM317, see 317 datasheet) and a DMM.
Design LM317 Constant Current Source Circuits
You need to have a dual-lab-supply with adjustable voltage and current limit (set to 200mA) for testing.
A functions generator and an oscilloscope will also be very useful.
If you don’t even have any of those, I can only suggest you leave this project for now until you have enough equipment and experience.
And I’d rather be honest.
Cheers,
Patrick
We’ll see how much we can help; But we cannot spoon feed, and certainly not remote debug.
Having said that, a Beta 22 is not much simpler either.
But if you have no understanding of circuitry, then maybe you should not attempt any of our projects.
All NPN & PNP transistors should be matched, including SOT23s and TO220s.
You can do that with a decent DMM which has an hfe-measurement function.
You need min. 50 pcs each for the Toshiba’s, and 20 each for the Sanken’s.
The left-overs from the amp are then used for regulators.
And you will need to have a SOT 23 test socket.
I personally match everything else, including all resistors and caps.
You should at least use 0.5% resistors all over.
Power resistors are best matched using a constant current source of 150mA (made up using a LM317, see 317 datasheet) and a DMM.
Design LM317 Constant Current Source Circuits
You need to have a dual-lab-supply with adjustable voltage and current limit (set to 200mA) for testing.
A functions generator and an oscilloscope will also be very useful.
If you don’t even have any of those, I can only suggest you leave this project for now until you have enough equipment and experience.
And I’d rather be honest.
Cheers,
Patrick
OK... Are you thinking that this crap (-80 db on 50 Hz and others up to 1 kHz) is normal, really?!!
This isn't bad PSRR, it's a full aberration of PCB.
p/s: another junk audio with amazing hum.
Attachments
![crappy headphones amplifier spectrum [SLHPA].JPG](/community/data/attachments/680/680107-0bbee4fd6cb420244b47cac8dd690222.jpg)
The measurement was made with a lab supply and no enclosure or shielding for the amp.
No doubt you know how to check with the spice model published what the PSRR is.
And the circuit only has current sources and emitter followers connected to the rails.
And of course none of those who has actually built has heard any hum from their phones.
Cheers,
Patrick
No doubt you know how to check with the spice model published what the PSRR is.
And the circuit only has current sources and emitter followers connected to the rails.
And of course none of those who has actually built has heard any hum from their phones.
Cheers,
Patrick
Thank you, I did not know this had already been adressed. I found the discussion in posts #97-100.
But one question, and please forgive my lack of knowledge: how did you arrive at the value of R_iv = 5.1K? The resistors R15,16 have that value, is it that easy? Or derived in some other way?
Gain = (R15 // R16 + R30) / (R7 // R8)
where // means parallel.
In the GB document, R15,16 are specified as 6.2k, giving a gain of 10.
But of course you can change those values for lower gain.
You also need to make sure there is enough voltage (> 1.3V) across R15,16 to bias the output followers.
The easiest for you is to try things out in Spice first.
Patrick
where // means parallel.
In the GB document, R15,16 are specified as 6.2k, giving a gain of 10.
But of course you can change those values for lower gain.
You also need to make sure there is enough voltage (> 1.3V) across R15,16 to bias the output followers.
The easiest for you is to try things out in Spice first.
Patrick
Hello Patrick,
I am attempting to adjust DC offset in an LT Spice model. I can use brute force, trial and error, and bring DC to almost zero. What I think happens... adjusting the CCS ultimately affects the quiescent current flowing through Q9,10 which in turn affects the quiescent current in the emitter-follower pairs.
My question, and please pardon my lack of knowledge, how was the value 5.1k calculated? I cannot see that in the schematics.
I am attempting to adjust DC offset in an LT Spice model. I can use brute force, trial and error, and bring DC to almost zero. What I think happens... adjusting the CCS ultimately affects the quiescent current flowing through Q9,10 which in turn affects the quiescent current in the emitter-follower pairs.
My question, and please pardon my lack of knowledge, how was the value 5.1k calculated? I cannot see that in the schematics.
> adjusting the CCS ultimately affects the quiescent current flowing through Q9,10
> which in turn affects the quiescent current in the emitter-follower pairs.
That is correct.
The output DC is measured at the junction of R19 & R20.
It is a combined effect of (any) DC offset at the gain stage and the emitter follower added together.
By trimming the current in the current mirror, both of the above are affected, as you rightly pointed out.
But the net effect should be that DC is zero at the output.
That does not necessarily mean that DC at e.g. R30 is absolutely zero also.
But it should be a small value, if all transistors are well matched.
In any case it has next to no effect on distortion performance because of the small offset values.
For example the trimming Morde had to undertake was 100k // 1k, or 1%.
And that can either be a result of differences in hfe, or in Vbe.
In my own build, the trimming was even less.
Hope I have answered your questions adequately.
Patrick
> which in turn affects the quiescent current in the emitter-follower pairs.
That is correct.
The output DC is measured at the junction of R19 & R20.
It is a combined effect of (any) DC offset at the gain stage and the emitter follower added together.
By trimming the current in the current mirror, both of the above are affected, as you rightly pointed out.
But the net effect should be that DC is zero at the output.
That does not necessarily mean that DC at e.g. R30 is absolutely zero also.
But it should be a small value, if all transistors are well matched.
In any case it has next to no effect on distortion performance because of the small offset values.
For example the trimming Morde had to undertake was 100k // 1k, or 1%.
And that can either be a result of differences in hfe, or in Vbe.
In my own build, the trimming was even less.
Hope I have answered your questions adequately.
Patrick
I attached a DC analysis for illustration purposes.
R43 has been used to trim the output DC to zero.
This is further illustrated by equal bias current through R19,20.
However, current through R15,16 differs by ~1%.
And this is due to the Vbe difference of the output Darlington's.
If you must, you can also trim DC offset by change the value of R15 instead of R43 to take care of the Vbe difference.
You will then be able to trim V1 (at R30) to zero also, in addition to Vout.
But this is normally not necessarily for BJT output transistors, as Vbe differences are small.
Trimming R43 only affects the DC operating point.
Changing R15 affects both DC and AC signal.
Hence my preference.
Patrick
.
R43 has been used to trim the output DC to zero.
This is further illustrated by equal bias current through R19,20.
However, current through R15,16 differs by ~1%.
And this is due to the Vbe difference of the output Darlington's.
If you must, you can also trim DC offset by change the value of R15 instead of R43 to take care of the Vbe difference.
You will then be able to trim V1 (at R30) to zero also, in addition to Vout.
But this is normally not necessarily for BJT output transistors, as Vbe differences are small.
Trimming R43 only affects the DC operating point.
Changing R15 affects both DC and AC signal.
Hence my preference.
Patrick
.
Ahhh... that is the missing piece of the puzzle. You provided the gain equation earlier, but I did not understand that Gain = R_iv. I was puzzled by that particular response,
, but it makes perfect sense now.I see that. The current differs by 20uA. I will be very happy if my build can accomplish such a small value. I will also be very surprised if it does!
That is good to know, but I will keep that in my back pocket and use it as a last resort. Now that I understand the detail, I should be able to calculate required values. I think that is the better way.
Thank you very much for the detailed explanation, as it clears things up nicely. Many thanks.
Mike