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class A Buffer
class A Buffer
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Old 16th July 2015, 04:54 PM   #21
AndrewT is offline AndrewT  Scotland
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the lower half is the 2Q CCS. It does not affect the bias voltage on the mosFET gate.

for a resistor loaded Follower I would suggest less than -12dB, maybe even a low as -20dB.
For CCS load Follower, -12dB should keep the harmonic at pretty low level.
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Last edited by AndrewT; 16th July 2015 at 04:57 PM.
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Old 16th July 2015, 07:01 PM   #22
sgrossklass is offline sgrossklass  Germany
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I've played with such a buffer a bit more. Looks like you want to keep away from the positive rail a fair bit (input capacitance nonlinearity seems to be the problem as things worsen at HF, so decreasing source impedance helps as well). Distortion into high-impedance loads tends to be minimum if steady-state output DC voltage is little more than needed for the respective output amplitude. So there's definitely a tradeoff between maximum level and distortion. In light of this you probably don't even want a DC-coupled output.

The distortion sims further up in this thread were taken with a circuit biased fairly high. This probably makes performance look worse than it would have to be. At ~10 mW into 400 ohms, 100 mA, 24 V supply, output biased at 4.83 V, and 1k source impedance feeding an IRF510 with ideal CCS, I'm getting -109 dB (2nd) / -120 dB (3rd). With a 15 V supply, it's a still-decent -92 dB (2nd) / -104 dB (3rd).

Last edited by sgrossklass; 16th July 2015 at 07:30 PM.
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Old 16th July 2015, 07:15 PM   #23
misterzu is offline misterzu
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Current sink in source is only half job.. if you move current sensing resistor (R5) to FET's drain, replace Q1/Q2 with PNP (Q2 moved to up) - you'll get much more linearity cuz whole circuit will turn into current sink, like in mine amp (this trick works with FETs too). Also like there additional current sink then will even more improve linearity:
class A Buffer-linear_follower_fet-png
Microcap says THD will be 0.00012% and its probably true (with BJT it really works fine in reality). Also in reality it can be necessary to add capacitive load decoupling filter on output (RL or simple R) to avoid oscillation.
And its possible to care about thermodynamic distortions and Early effect with ''double' follower, but this will take some 'fee' of voltage loss.
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File Type: png linear_follower_fet.png (12.4 KB, 377 views)

Last edited by misterzu; 16th July 2015 at 07:32 PM.
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Old 17th July 2015, 08:02 AM   #24
AndrewT is offline AndrewT  Scotland
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Quote:
Originally Posted by sgrossklass View Post
.....................I don't think that factor-of-4 rule of thumb really applies to CCS-loaded followers. With the CCS the main source of voltage depence has been just about eliminated, and distortion into higher-impedance loads is much improved. ......................
Quote:
Originally Posted by sgrossklass View Post
.................At ~10 mW into 400 ohms, 100 mA, 24 V supply, output biased at 4.83 V, and 1k source impedance feeding an IRF510 with ideal CCS, I'm getting -109 dB (2nd) / -120 dB (3rd). With a 15 V supply, it's a still-decent -92 dB (2nd) / -104 dB (3rd).
Quote:
Originally Posted by AndrewT View Post
................for a resistor loaded Follower I would suggest less than -12dB, maybe even a low as -20dB.
For CCS load Follower, -12dB should keep the harmonic at pretty low level.
Despite your alleging in post20 that the rule of thumb is flawed, your simulations in post22 supports my original contention.

Keep the absolute maximum well above the normal audio maximum.

10mW into 400ohms is 2Vac
for the +-15Vdc sim version this is ~-14dB headroom. (2nd harmonic distortion has increased by 17dB rel +-24Vdc)
for the +-24Vdc sim version this is ~-18dB headroom.

I wonder what the +-12Vdc sim would show for the same 10mW into 400ohms?
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Old 18th July 2015, 10:23 AM   #25
sgrossklass is offline sgrossklass  Germany
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But your rule of thumb alone won't help much, as bias setting tends to have a far greater influence than input level by itself. I'd say it's mainly important that you keep the input at least 3 V or so away from the positive supply and Vgs + ~1 V ~= maybe 5 V away from the negative supply at all times, so you could get a decent 7-8 Vpp on a +15V supply or 15-16 Vpp on +24V.

(RJM's sim used a +15 V supply while biasing the input at ~+12 V, and you can probably imagine what that means if you go in with a 2.83 Vp signal. Something like +8.5 V would have been much closer to optimum. That potentially is quite a change from a resistor-loaded follower.)
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Old 18th July 2015, 04:42 PM   #26
doors666 is offline doors666  India
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Quote:
Originally Posted by AndrewT View Post
R11 & 12 look quite low. You don't need 10 to 12mA for a mosFET bias circuit.
The Blue LEDs would be better replaced with 4, or 5, Red LEDs. 1mA to 2mA would be enough for the Red LEDs allowing 1k, or more, to be used.
Any particular reason for using red. I prefer the blue color and less points of failure is better as any led failing will expose the headphones to significant dc.

Quote:
You might need a base stopper or two to stabilise the 2q CCS
You mean at the base of Q1? I did have a 100 ohms there but some people reported in some threads that at times that resistor causes instability and i took it out.
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Old 18th July 2015, 05:14 PM   #27
AndrewT is offline AndrewT  Scotland
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The low voltage LEDs have less noise.
They may also have lower dynamic impedance.
Generally a string of red LEDs is a better voltage reference than a Blue or White LED.

There may be a case for using IR LEDs and include one red as an indicator.
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Old 18th July 2015, 11:01 PM   #28
sgrossklass is offline sgrossklass  Germany
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Hmm. Looks like MOSFET models vary greatly in accuracy. The stock IRF510 and IRFP240 models predict nonlinear capacitance related distortion that is an order of magnitude lower than the stock IRFZ120R model or Bob Cordell's IRFP240 model. Which results am I to believe? I suspect it's the latter ones that are correct...

Anyway, with a 10 kHz (!), 4 Vpp signal into 400 ohms and the IRFZ120R with a real CCS (2T similar to RJM, BC337-25 + 2N3055, 96 mA) at +15 V supply, I'm getting the following harmonics depending on input bias point:
7.4 V (min unclipped, the CCS likes >=~1 V = 6.8 R * 95 mA + Vce,sat): H2 -55 dB, H3 -72 dB
9.5 V: H2 -49 dB, H3 -64 dB
12.3 V ( la RJM): H2 -36 dB, H3 -45 dB

So clearly, the choice of bias point can make a difference of up to an order of magnitude here. (For comparison - for each 10 dB level decrease, H2 goes down by 10 dB and H3 by 20 dB. So getting H2 down an order of magnitude at same bias point requires reducing signal by an order of magnitude.)

Reducing source resistance from 1k to 10 ohms gives H2 of -73 dB to -90 dB instead, approaching the expected 40 dB reduction. So clearly, power MOSFETs want to be driven hard at higher frequencies. In practice we are often seeing gate stoppers of 100-220 ohms, which I guess is because speaker power amps are much more current limited than our little Class A follower and operate at much higher supplies to boot.

So let's test at +24 V instead:
7.4 V: H2 -69 dB, H3 -91 dB
12.3 V: H2 -63 dB, H3 -84 dB
16.3 V (output at +12 V): H2 -55 dB, H3 -73 dB
21 V: H2 -36 dB, H3 -48 dB

This thing is starting to look quite good even, but definitely prefers bias levels that put the output below midpolnt, ideally as far as the current source will permit at maximum signal amplitude.

So I chose the smallest p-channel MOSFET that the stock LTspice library would offer (BSS84) and put in a small buffer in front of the main FET with a 10k load resistor.
Bias +14.2 V (output at +12 V): H2 -72 dB, H3 -90 dB
17 dB less 2nd harmonic, not bad for a fairly minimal increase in complexity. A BC557C with a 10 pF Miller cap does about the same, maybe a dB worse.

So I put in an ideal CCS of 726 A to replace the 10k (still with BC557C in), and...
Hey presto, H2 -82 dB, H3 -100 dB. We're seriously entering blameless territory.
(This time around, the BSS84 fares a bit worse, at -79 / -96 dB. Lower transconductance = higher output impedance in a follower.)
You could also go AC-coupled and use an npn / n-JFET / whatever.

Of course you could also use a boring old opamp follower (isolation resistor advised, capacitive load and all), but where'd be the fun in that? Besides, types with good capacitive load driving tend to use a bit more power than a little follower.

Back to +15V, same currents... best-case biasing for 4 Vpp (output DC at +3 V) gives H2 -83 dB, H3 -96 dB (down from -55 / -72 dB - THD wise that's going from about 0.2% to <0.01%). Clearly a 2-stage buffer is looking quite alluring.

Determining optimum "buffer buffer" current is left as an exercise to the reader.

Last edited by sgrossklass; 18th July 2015 at 11:24 PM.
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Old 19th July 2015, 07:40 PM   #29
sgrossklass is offline sgrossklass  Germany
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On to misterzu's circuit:

One of the things that I like about the plain MOSFET follower is its relative immunity to capacitive loading, and that may get lost here. But anyhow, let's simulate it:

I used IRFR120Z as before, BD140, 2N5551 and 1N4148 (Cordell). Same 10 kHz, 2Vp, 1 kOhm input and 400 ohm load as before.

Umm... sorry buddy, but that one sims with far from ppm-level distortion under these conditions. Somewhat worse than the plain CCS-loaded follower, in fact, as output towards the negative rail is a bit more restricted, and it looks like PSRR may suffer up top. (I assume it'll react more graciously to output loading though.)

+15 V supply:
7.4 V: H2 -54 dB, H3 -59 dB (onset of clipping)
8 V: H2 -51 dB, H3 -67 dB
9 V: H2 -48 dB, H3 -63 dB
12.3 V: H2 -31 dB, H3 -39 dB

Results at +12 V are expectedly worse. As I anticipated, the circuit is not at all happy when I add 10 nF of capacitive load - the threshold of oscillation is between 2n2 and 3n3. Rather marginal when headphone cables can have up to ~1 nF. By contrast, the plain buffer (even with pre-buffer) remains unimpressed even at 100 nF.
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File Type: asc MOSFET follower misterzu 1.asc (3.1 KB, 23 views)

Last edited by sgrossklass; 19th July 2015 at 07:44 PM.
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Old 19th July 2015, 08:53 PM   #30
misterzu is offline misterzu
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Compare with lower load resistance. On my pic it is 60 Ohm
From my sim (and in reality for BJT) mine circuit produces 0.00012% THD on 1V on 60 Ohm load while has ~130mA total current consumption from 12V PSU. And CCS-loaded follower with same load/PSU numbers produces 0.06% of THD.
Sure for 400 Ohm load 100mA of quiescence current enough to compensate Vbe (or in case of FET - gate threshold) variations caused by drain current deviation that is 2/400 = 5mA of 100mA and my circuit doesn' have much benefits due to more active elements involved.. But lowering load resistance to 60 Ohms things will change: 33mA deviation of 100mA quiescence causes huge gate threshold variation and - distortions. Mine current-around-feedback essentially stabilizes drain current so it has its benefits when load currents comparable to quiescence current. There however some other side-benefits too: limited short circuit current and constant current eaten from PSU, that effectively excludes PSU from signal path (so PSRR will improve actually).
About capacitive load - yes, as I wrote output filter is recommended. For example 2Ohm resistor or 1uH + 33 Ohm in parallel will completely fix that problem. However on practice simple follower that has high enough input impedance also sometimes tends to oscillate, sure less then mine circuit but still can require additional frequency compensation or output filter. I saw oscillation of stupid Darlington pair loaded with single resistor (and be sure that power decoupling was OK). Not sure about reasons, but have few ideas about this: at first, follower itself has inductive kind of output resistance on high frequency (see http://www.radioeng.cz/fulltexts/1997/97_01_05.pdf for example) that together with capacitive load forms oscillatory circuit. Another idea is stray EMI feedback between output and input that can cause enough level amplification together with phase delay.. So this problem is not belonging exclusively to mine circuit

Last edited by misterzu; 19th July 2015 at 09:16 PM.
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