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xrk971 11th April 2019 02:16 PM

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The paths of the SMT prototypes were indeed tight and small. Jhofland did a great job on keeping the design tight to minimize the loop current area. Here is a closeup of the SMT active bridge. It doesn't get much tighter than this:

For the SLB, we wanted to make it accessible to the average DIY'er who doesn't want to do SMT soldering. So compromises had to be made with using four TO220 MOSFETs, spacing is larger, DIP 8 version of LT4320, etc. But I think it should be all good. I will order a set of verification boards and test to make sure there are no extraneous switch noises or oscillations etc before releasing the final (verified to be working) board for the GB. This extra level of work and due-diligence is what gives the DIYA community the peace of mind that they won't be getting a dud. It's a lot of extra $ and work but worth it in the end.

Mark Johnson 11th April 2019 02:52 PM

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The LT4320 datasheet gives customers all the data they need, to calculate turn on and turn off time. The MOSFET gate drivers, which are output pins on the LT4320, have a Thevenin equivalent circuit that is definitely not an ideal voltage source. External resistors in series with the MOSFET gates would be superfluous.

And, if it so happens that Linear Technology offers an LTSPICE model of the LT4320 (?), I expect their model gets this important detail exactly right. Pair it with a MOSFET spice model that actually does simulate Qgtot = 150 nC, and you get an acceptably accurate simulation of turn on and turn off. Plot the current waveforms and look for fast transients / high frequency components if you worry about those. Plot MOSFET power dissipation if, like me, you are concerned about that.


jwjarch 11th April 2019 06:37 PM


Originally Posted by xrk971 (
Thanks for self organizing the interest list Jwjarch!


baswamin 12th April 2019 03:05 AM

SLB Group Buy List
baswamin - 2 boards
meanie - 2 boards
jwjarch - 2 boards

SemperFi 12th April 2019 09:06 AM

Mark is right, certainly not a power house of a driver. So there will not be much EMI from the gate drive which is good news. But a quick test in LTspice with a 140nC FET shows it a bad idea, it cannot drive the gate more than 4-5V, and at that gate voltage the Rds-ON is not as low as it can be. Might as well use FETs that have lower Qg so they will be driven properly and you get low enough Rds-ON.
I think when selecting FETs you want low enough Rds-ON, not unecessary low. That way you select for each load. One load may draw 1A, another 5A etc. Dont use same beefy device on both.

xrk971 12th April 2019 02:30 PM

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We have revised the schematic to include a 47pF capacitor between the collector and base of the master BJT and a 10R resistor between the emitter of the master BJT and the output. This will give us an opportunity to squash any oscillations, should they arise. Board layout outline size remains the same size. Parts list (BOM) is also attached below.

Mark Johnson 12th April 2019 03:47 PM

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Our simulations show that the CFP topology should be even better.
You probably want to run them again, including the two new components in the CFP output stage. You've cut its effective gm = dI/dV by about a factor of 5x, and I imagine there is a very real possibility this will impact your measures-of-goodness. The ways you quantify "even better" in the quote above.

The response to a square wave of output current will be affected, to name one example. Whether the difference is small enough to be disregarded, is a human decision.

You might not get a great deal of Miller Effect from the new 47pF capacitor, since it's effectively voltage driven rather than current driven. Open loop simulations with, and without, that capacitor will tell you how much it does or does not help.


xrk971 12th April 2019 04:11 PM

The idea was to have those positions available in case we see oscillation - but will initially leave unpopulated. As I said, our earlier tests with the CFP cap Mx had issues with oscillation. We will redo the simulation though to make sure performance is not too negatively impacted.

xrk971 13th April 2019 12:56 AM

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Some more data running a real amp as load. This time with is oscope ch1 on output of cap Mx and Ch2 on input to cap Mx (after active bridge and CRC). For 4.35A and 27.5v to the amp. Getting 99mV rms ripple which looks almost sine wave like, and 3.3mV rms downstream of the cap Mx. This is the Darlington variant.

gary s 13th April 2019 06:37 AM

Nice project X, just to be clear - one PCB will do a +/- dual supply for a typical power amp of say 20 to 30 watts class A.

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