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GB for Virtins MI Pro for RTX6001 autoranging/autoscaling & for soundcard end users

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Thank you for your patience, Virtins.

I used a combination of figure 1 & 2 with adding a capacitor to protect the output of RTX (I feed the reg with 17Vdc input, the output of reg is 14.5Vdc).

For example, with 0.2A reg load, how AC stimulus must I used?
The following capture is with 1Vac Stimulus (with very draft wiring).

It is still not good, I am still wrong!
 

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The AC injection method in the power supply PSRR test is a little different from the power supply impedance test. In Method 2, the former needs to add an inductor in series to the DC power supply to prevent the AC voltage being shorted by the DC power supply's internal impedance, while the latter, in contrast, needs to force the AC injection current flow through the DC power supply's internal impedance.

In your above test, the injected AC voltage is 1 VACpeak, but the measured one at the power supply's input is only about 20mVpeak, probably shorted by the low impedance of the DC supply (no AC blocking inductor added?). The low injection voltage will limit the measurement accuracy, especially when a non-frequency-stepped-sine stimulus is used.
 
I hadn't input an inductor in Method 2, only the capacitor C on generator output.
What kind (characteristics) of inductor can I use in series?

I would like at the first to have some good results with method-2 and then I am thinking to try the method 4 with a lundhal 2:1 transformer that I have.

Thanks.
 
Because, The L and C will create a HPF for VAC which will limit how low in frequency we can measure the PSRR, I saw from a L-C Filter Calculator (L-C Filter Equations) that with 1000uF capacitor that I used...I need a large inductor to measure low.
Quickly, I took an 10mH inductor that I had on my lab and with the calculator I saw that the cut-off is 1.5KHz
The new capture is better but I can't understand at this example how to estimate the dB of PSRR (red graph), because the graph goes upper and down of the 0dB.
 

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If L=10mH, C=1000uF, I got a cut-off frequency about 50Hz using the above L-C filter calculator link you provided. You got 1.5kHz ???

At 50 Hz, the impedance of L is 2*3.1415926*50*0.01=3.14 (ohms); the impedance of C is 1/(2*3.1415926*50*0.001)=3.18 (ohms). Assuming the impedance of VDC is zero, and there is no capacitor on the input side of the DUT (Cin in Method 2) and no load at the DUT output, then the AC voltage at the input of the DUT would be about 3.14/(3.14+3.18+50) * 1V = 0.056 V. If you change the VAC amplitude from 1V to 10V, then voltage will become about 0.56V. This will increase the measurement SNR.

BTW, the red line in the above bode plot is the phase shift, you can hide it to show only the gain (PSRR). To hide the phase display, click the spectrum analyzer window, and select "Off" in the selection box on the right-hand side of "P" (Phase) at the bottom toolbar of the screen.
 
I will repeat the testing according to you.
Normally, there is a capacitor on input side of LDO of 10uF low ESR.

Sure, the 1.5KHz comes with some errors to zeros on calculator!
I see a 1591.5Hz if the zeros numbers are wrong!

I thought that must look at the red graph that is the right input of ADC (LDO AC stimulus output).
 
The impedance of the Cin (=10 uF in your case) at the input of the DUT is 318 ohms @50Hz and only 0.318 ohms @50kHz. It will greatly suppress the input VAC and, as a result, the measurement SNR at high frequencies. It should be removed IMO because its effect can only be measured in two steps, with and without it, and here it is the DUT's PSRR to be measured. It is removed in Method 3 which is recommended by TI (http://www.ti.com/lit/an/slaa414a/slaa414a.pdf).
 
Virtins,
I had thought in my mind, to try different layouts on LT3045 LDO (with this PSRR test), to find what PCB have better PSRR design.

Today, I take measurements with the figure-2, with and without Cin on a specific layout PCB.
The value of L was 10mH.

Really, I have confused with the results of graphs...I can't understand what it happens here!
Of course with Cin on pcb the output voltage is right (5V input->3.3V output), without Cin there is no good regulation (5V input->2.5V output that varies around of 2.5V).
I used a Rigol DP832 as Voltage Source for power the LDO.
The electronic load set to 100mA.

At the first measurement of "PCB-1, with C", the value of Cin is 10uF. I see 162.7mVac stimulus on input and 103.3mV on output.
At the second measurement of "PCB, without C" the Cin has removed. I see 2.34Vac stimulus on input and 111.2mV on output.
Quickly it seems to be better rejection on PCB without C1.
It couldn't to be true!
 

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Here are two measurements with the same parameters on two different PCB layers designs.
The capacitor Cin is ON.
Can we conclude that the graph with bigger gain has more PSRR sufficiency from the other?
 

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What is the AC RMS value at the DUT's output if the AC stimulus is zero?

To troubleshoot, you can use a sine wave instead of white noise, and change the Bode Plot back to Amplitude Spectrum. Use DDP viewers to display f1RMS_A(EU) and f1RMS_B(EU). The ratio of these two values is the PSRR at that particular test frequency.
 
What is the AC RMS value at the DUT's output if the AC stimulus is zero?

- With the PCB of post #568, I see 694-706uV (it varies) - see the attachment.

To troubleshoot, you can use a sine wave instead of white noise, and change the Bode Plot back to Amplitude Spectrum. Use DDP viewers to display f1RMS_A(EU) and f1RMS_B(EU). The ratio of these two values is the PSRR at that particular test frequency.

- Nice,
With 500Hz sine the Ch.A (input) has 81.46dB and the Ch.B has the 71.87dB (output).
a) What is meaning of this, the input has more PSRR from the output of specific layer PCB?
b) What's wrong with my calculation on PSRR?

The measured PSRR seems to be very low compared with 75¬115 dB in 10Hz¬100kHz in the datasheet of LT3045.

- You have right, but they are the results with WhiteNoise, now!
 

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Thanks for the residual output ripple information. It is about 0.7mVrms.

Assuming that the highest PSRR to be measured is 120dB, a 1mVrms output ripple would require an injection of 1000Vrms at the DUT's input. This is not feasible. On the other hand, the residual output ripple without a stimulus is already 0.7mVrms. It prevents us from using a lower injection voltage in this broadband stimulus method.

It looks like we have to switch to the frequency stepped sweep method using Device Test Plan in order to improve the measurement SNR. We can extract the RMS value of the single-frequency test signal and exclude all noises outside this narrow-frequency band to improve the measurement SNR. I think, the residual ripple can go down to the order of 1uVrms using this method. This corresponds to 1Vrms stimulus at input if the PSRR is 120dB. A device test plan for this method will be provided in one or two days. You can try it with a single-frequency sinewave first to see how it performs.

In your 500Hz test, the spectrum analyzer shows severe spectral leakage with Rectangle window. You can change it to Kaiser 6. Also, you can use a larger FFT size such as 131072 or 262144. The Y scale can be set to dBV. With the Y scale in dB, dBV or dBFS, the PSRR UDDP should be defined as: [f1RMS_A(EU)]-[f1RMS_B(EU)]. However, even if you change the above setting, from the waveform displayed in the oscilloscope, the PSRR at 500Hz looks still very low, probably less than 20dB. Maybe somehow the input was coupled to the output without going through the DUT in your test?
 
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Device Test Plan for Bode Plot Measurement with Autoranging

Attached is the Device Test Plan for Bode Plot measurement using frequency stepped sinewave sweep, with autoranging. It contains four files:

1. BodePlotFrequencySteppedSine_RTX6001.dtp
the Device Test Plan file, to be put under \dtp subdirectory.

2. BodePlotFrequencySteppedSine10s_RTX6001.psf
the Panel Setting File for test frequencies in 1Hz ~10Hz, to be put under \psf subdirectory. The sampling duration is 10 s.

3. BodePlotFrequencySteppedSine1s_RTX6001.psf
the Panel Setting File for test frequencies in 10Hz ~100Hz, to be put under \psf subdirectory. The sampling duration is 1 s.

4. BodePlotFrequencySteppedSine100ms_RTX6001.psf
the Panel Setting File for test frequencies in 100Hz ~96kHz, to be put under \psf subdirectory. The sampling duration is 100 ms.

If you want to do troubleshooting, you can load one of the above PSF file without loading the device test plan to test the PSRR at a single frequency.

The test frequencies are designed to be at the center frequencies of 1/3 octave bands from 1Hz to 96kHz, 50 test frequencies in total. Independent autoranging for Ch. A and Ch. B is in place. The VACpeak is set to 10V.

Variable definitions in the device test plan:
X1: test frequency, initialized to be 0.976562 Hz in Step 5. will step up at a step of 1/3 octave.
X2: VACpeak, initialized to be 10 V in Step 4, fixed.
X3: VDC, initialized to be 0V in Step 3, fixed.
X4: Ch. A Input Range, initialized to be 0.1414V in Step 6, autoranging
X5: Ch. B Input Range, initialized to be 0.1414V in Step 7, autoranging

The attached picture is obtained from a loopback test using the device test plan. Basically it measured almost 0dB gain and 0 degree phase shift for all tested frequencies.
 

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