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|5th February 2020, 09:11 PM||#1|
Join Date: Sep 2006
A constant-Ic β-tester: β-Master 🌈
This tester was developed as a spinoff from this thread:
Constant Collector Current hFE Tester for Transistors
The circuit proposed proved too complex for the OP, but I decided to bring it to completion anyway: it is probably a useful piece of kit for many DIYers.
The complexity, especially in its finished form, might look daunting, but that's kind of inevitable with this type of instrument: many parameters need to be made variable, and being a transistor tester, it has to accommodate both sexes, which brings another layer of complexity.
That said, the complexity is relative, and no expensive component is required.
It can be built as a naked board, with an external supply and multimeters as indicators, or as a complete, self-contained instrument (or anything in-between).
It does have some attractive features: it covers most of the needs for DIY use, with an Ic range of ~150µA to 1.5A, a Vce of 0 to 10V, requires a single unipolar supply, and the switches for the range and polarity are ordinary DPDT types (one has a center OFF).
A constant Ic tester is very convenient compared to alternatives improvised with supplies for example: comparisons are immediate and straightforward.
The direct-reading is also very convenient.
I didn't build and test a complete instrument: I just breadboarded the functional core for NPN (which operated as expected), and I also tested critical sections, like the polarity handling meaning the project is relatively safe.
The complete instrument has been tested in sim, and is functional (I include the .asc).
Note that this is a DIY-grade instrument, not a lab reference, but with care in construction and a good calibration, it is OK for a +/-1% accuracy, which is ample for a parameter like β.
Comparisons can be made with a greater accuracy.
This is the circuit:
And a sim showing the measured value against the actual value (β+1 because what is actually measured is the ratio of Ie to Ib, not Ic/Ib):
|6th February 2020, 04:48 PM||#2|
Join Date: Sep 2006
Here is a short description of the circuit:
The test current is generated by variable CCS's built around Q3 to Q6. The current feeds the emitter of the TUT, because it is more convenient than the collector, but in general, it will rarely matter: the displayed value will be β+1 rather than β, which makes practically no difference, except if the β value is exceptionally low, in which case one just needs to subtract one to the result, something that does not require an exceptional mental agility.
I have opted 15mA - 150mA -1.5A full scale, but it is perfectly possible to chose other values, or use a single range.
The Vce is also variable, and has its dedicated regulators.
The resulting base current of the TUT is converted to log thanks to Q12/13 and in parallel, a scaled image of the emitter current is logged by Q10/11.
The chosen scaling factor is 100, because it is a good median value for the β of ordinary transistors: it allows the logging transistors to operate at ~comparable current densities, which is desirable for a good accuracy.
The difference between the two log values is then converted by the differential antilog converter Q14->17 and U2. The converter is not fully balanced: the real antilog work is performed by Q16/Q17 only, with the rest providing compensation.
Taking the difference of two log values is equivalent to the quotient of the initial values, but the scale of the output needs to be referenced somewhere.
R14/15 with the 12V supply set the output at 1V when the log difference is zero, ie when the β of the TUT is 100.
The circuit can be calibrated by shorting TP100 and adjusting R15 (something I forgot to do in the sim, which is why the measured values are slightly too low).
There is no output offset adjustment, because offset errors are converted to span by the antilog circuit, meaning the span adjustment is theoretically sufficient to compensate all errors.
Theory and practice are somewhat different though, and precautions and corrections are required: the differential antilog converter has a single output, but it is not really single ended: its output is polluted by the log common-mode of the input.
The voltage is small, in the tens of mV, but it will degrade the accuracy especially for low β values.
U1 measures the CM wrt. ground and corrects the output of U2.
Internal errors cannot be corrected, which is why a precision opamp is required for U2.
The supply is a good, accurate 24V which is necessary because the supply voltage directly impacts the output.
Q18/19 split this supply to provide a low-impedance local ground.
If the supply source is an accurate, stable 24V, U4 can be omitted.
|7th February 2020, 05:57 PM||#4|
Join Date: Sep 2006
I hope so, now some practical considerations:
If the β-meter is built exactly according to the example, it will need (and thus dissipate) a significant amount of power: in excess of ~40W.
Some of that power will go into the voltage regulators, another part will be handled by the CCS and its emitter resistor, and finally the TUT itself will heat up considerably: at the max Vce-Ic, this would be 15W.
Substantial heatsinking is thus required, including for the TUT, perhaps especiallly for the TUT: even if it tolerates 150°C Tj, it is preferable to attach it to an ~infinite heatsink.
No need for huge extrusions or liquid cooling: the thermal resistance needs to be ~zero just for the time needed to make the measurement, a few seconds at most.
This means that a copper or aluminum block sufficiently massive can present a sufficiently low thermal impedance short term to make valid measurements.
Pulsed measurements are another option, and the βmeter could easily be modified to operate at a low duty-cycle. A µcontroller would be the logical choice to implement that, but two or three common analog circuits could do it as easily.
I may publish an extension later.
On the schematic, the dotted lines indicate the matching/thermal tracking relationships, and there are a number of them!
To attain the advertised performance, it is essential to respect these pairings.
The input transistors of the CCS's and their compensation have to be selected and matched, and in thermal contact, but well clear of the rest of the CCS: the emitter resistors and the power transistors.
The logging transistors Q11/13 and Q10/12 have to be carefully matched, and mounted in close thermal contact to ensure a proper, offset-free balance.
Q14 to Q17 being duals, they are inherently matched, but they need to be in thermal contact with the logging transistors, to cancel the effect of kT/q, the thermal voltage.
As a consequence, it is probably simpler to attach Q10 to Q17 to the same chunk of copper or aluminum: the collectors are common and grounded, and dual transistors have an isolated case.
R24 and R25 define the internal ground, and should be well matched because the resulting 12V is used as a reference.
It is important to remember that the output voltage representing β becomes negative for PNP transistors: with digital displays, that is not a problem, but if an analogue meter is used, the polarity switch will also have to reverse it.
|9th February 2020, 03:33 PM||#5|
Join Date: Sep 2006
I have developed the pulse extension, but first here is the corrected DC version, tweaked and calibrated (virtually) in .asc.
This shows the operation of the pulse extension, but behaviorally only: I don't have models for the CD4053.
I also include the .asc (BetamgP)
This is the physical circuit, based on the CD4053:
One of the operators is wired as an oscillator and the two other freeze the value on the output amplifier when the circuit is idle.
The dual optocoupler inhibits the CCS's during the inactive phase.
The frequency of operation is around 10Hz, and the duty-cycle is <4%, meaning a maximum dissipation in the TUT reduced from 15W to a little more than 0.5W.
I have used optocouplers, because the circuit needs to work for both polarities (and I was a bit tired and lacking inspiration).
A switch allows pulsed or DC operation; DC mode makes the Ic measurement easier.
The circuit has not been tested as a whole, but each function-block was.
|10th February 2020, 05:57 PM||#6|
Join Date: Sep 2006
The total supply voltage has to be 24.0V. Connect a voltmeter between the 24V TP and the (-) of the input supply; adjust R30 to read 24V.
The ratio of the output current to scaled current should be exactly 100.
Position P1 halfway, and for each current range measure the collector current by connecting an an ammeter between the E and C terminals of the tester.
Connect another ammeter across Q10 or Q11, and adjust R10->12 to read exactly 1/100 of the collector value.
With an ordinary transistor inserted, 150mA range P1 halfway, short TP100 and adjust R15 to read 1.000V at the output.
To check that all offsets (transistors, opamp) are under control, R13 can be replaced or paralleled to arrive exactly at the value of R14 + R15 (great accuracy is required) (TP100 still shorted).
The value at the output should not exceed +/-2~3 points of β (1point = 10mV).
If it is larger, there is a problem with the matching of the dual transistors or the offset of the opamp.
Resilience to miswiring, wrong polarities, etc.
The tester itself will tolerate any insertion or polarity error, or defective TUT without failure, and will protect the TUT for some situations, but not all.
I am not going to examine each case, but just an example: even a good transistor, of the correct polarity and correctly connected can be destroyed: if you test a BC547 at Ic=1A Vce=10V, it will be fried instantly.
There are many more ways of frying a good transistor, and there is no protection for that, except care and attention: you should always double-check the connection and settings before firing up the tester
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