One way to lower the higher harmonics of ES9038Q2M is to lower the DAC clock albeit with some increase in noise floor.
Here is the same setup with 11.2896MHz clock (earlier was 45.1584MHz). Also the input is now -1dBFS. With these changes the result meets PMA's requirements
Yes, this looks good and it keeps good dynamic range (low N).
If I'm not mistaken Khadas also ditched the Vref op amp buffer in Tone2 Pro with considerable improvement to both THD+N and IMD (no hump).
Not necessarily. Have you tried the synchronous mode? It could be interesting to compare the results.
I have 45M/49M clock in my setup so synchronous would require 352k/384k sampling rate. Unfortunately REW is not up to this in Linux. I need to change the clock to 22M/24M for 192k sampling rate.
Synchronous mode can work with higher frequency clocks works so long as they are integer multiples of the minimum synchronous clock frequency. IIRC ESS told the Twisted Pear guys about that. Alternatively, the internal MCLK divider can be used to lower the internal clock frequency.
As an aside, these DACs tend to sound better in synchronous mode, or at least if in asynchronous mode, then with DPLL_Bandwidth set to the minimum stable value as ESS recommends. DPLL_Bandwidth very stable at a setting of 0x01 can sound similar to synchronous mode.
Also, and again IIRC, a lot of the conclusions KSTR posted at ASR about ES9038Q2M has been known by Allo for a long time, at least in practice. They know about slight filtering before the I/V opamps, not enough to cause gain peaking issues, and they use further passive filtering before the difference stage. The latter stage was found to be more sensitive to RF noise, perhaps since its inputs operate in common mode. To be clear, not saying Allo looked at residuals, just that they figured out what works using the instrumentation they have, and by listening.
As an aside, these DACs tend to sound better in synchronous mode, or at least if in asynchronous mode, then with DPLL_Bandwidth set to the minimum stable value as ESS recommends. DPLL_Bandwidth very stable at a setting of 0x01 can sound similar to synchronous mode.
Also, and again IIRC, a lot of the conclusions KSTR posted at ASR about ES9038Q2M has been known by Allo for a long time, at least in practice. They know about slight filtering before the I/V opamps, not enough to cause gain peaking issues, and they use further passive filtering before the difference stage. The latter stage was found to be more sensitive to RF noise, perhaps since its inputs operate in common mode. To be clear, not saying Allo looked at residuals, just that they figured out what works using the instrumentation they have, and by listening.
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Better to you? OK, fine. But what does that really mean for the quality of sound replaying device? As the saying goes, one man's trash is another man's treasure. Without a reference point, saying that something is better doesn't mean anything to others who weren't there when you listened to it.
You can use sox for the generator, instead of REW at higher samplerates, if the generator part causes glitches. Works very good IME.
You can of course keep the op amp buffer but you really should think about replacing Spectraplus if you care about accurate results
The software mentioned calculates THD+N (SINAD) wrong. Noise is not properly involved and it shows too optimistic results.
I know that SPlus has wrong THD+N calculation (which was never interesting for me, instead of THD), but the harmonics level is accurate.
This seems to be correct. Here is the CCIF@192k with ES9038Q2M in synchronous mode using 49M MCK with divider 2. Also 96k and 48k work with this setting. The improvement is only marginal but maybe with a better clock more improvement could be possible.
Hi Bohrok2610,
Do you use ebay ES9038Q2M with external IV circuit or your own board to get this result?
My own board. My other DAC boards share the same format so they are interchangeable. Forget about ebay boards as most of them have design flaws which cannot be fixed by hacking.
It is part of a measurement setup / standalone dac I've been working on for my own use. The setup currently includes
Schematic of the DAC board in attachment. Some components are not according to schematic (e.g. board has OPA1656 as opamps and LP5907 regulators for DVDD/VCCA).
- STM32F723 based USBI2S bridge (I2S input & output) & controller. Shown e.g. here. Capable of 384k/32 play&rec and 768k/32 play.
- DAC boards (AK449x, ES9038Q2M)
- ADC boards (AK5394, ES9822PRO)
- SPDIF boards
- STM32F030 controller board for SPDIF standalone dacs.
Schematic of the DAC board in attachment. Some components are not according to schematic (e.g. board has OPA1656 as opamps and LP5907 regulators for DVDD/VCCA).