you mean we need to try this lib? Actually, I wondered, what is the reason to make FFT faster than we need? So far Tyoma(my son and coder, he's the left side of my avatar) implements all from the scratch, he didn't complain about the speed so far but anyway, thank you for the input.
ASRC in the ESS DAC will not change the generated output frequency, it will just calculate new samples in the pace of the DAC clock, instead of using the original I2S samples. The analog output signal will stay synchronous to the I2S stream, i.e. to the sampling ADC clock (if common DAC/ADC I2S clock is used).
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I would strongly advocate for isolated DAC and ADC. Please do not share supplies and ground. When they are shared its a constant battle to deal with unintended ground loops. A common controller would make software interface easier, just isolate between controller and ADC/DAC. This is the one weakness in both RTX and QA401 that could be easily addressed.
If the ASRC is recreating the clock can you run into problems using rectangular windows etc. if the synchronous clocks are not exactly synchronous?
If the ASRC is recreating the clock can you run into problems using rectangular windows etc. if the synchronous clocks are not exactly synchronous?
Demian, do you mean isolating DAC from ADC or isolating both from the USB line?
ASRC creates new samples which correspond to the pace of the output clock, it does not change the signal waveform with regards to the incoming clock. Plain FIFO makes the waveform asynchronous to the input clock but ASRC is the correct method of interfacing the two clock domains.
ASRC creates new samples which correspond to the pace of the output clock, it does not change the signal waveform with regards to the incoming clock. Plain FIFO makes the waveform asynchronous to the input clock but ASRC is the correct method of interfacing the two clock domains.
Yeah I followed the MQA debate a bit and while I would say that Goldensounds made some very good contributions, I struggle to identify his long-term competitive advantage in the audio review space. After all the audience is limited and there are already established reviewers out there. Having an APx555 and knowing how to make the usual measurements used to be somewhat of a unique selling proposition (as they call it in marketing) but that is not the case anymore. Nonetheless, I am interested in his review of your Cosmos ADC.
More generally speaking: If your goal is maximum exposure, you should send your ADC to Amir sooner or later. If you want the most thorough testing of your ADC, I think someone with the right measurement gear and the right technical background would be beneficial. Getting both from the same person seems to be wishful thinking in the current state of things. But then again, I don't know all the audio review people and their capabilities...
Really, for whatever reason I thought it is reconstructing the master clock starting from the LRCK and the async clock feed, using an internal fractional PLL (the so-called D_PLL). Not sure from where I got this, could be buried in the data sheet.
ASRC has fixed input clock, fixed output clock and creates a new stream of samples which carry the same waveform as the incoming stream. Various advanced algorithms allow "smoothing" the jitter of the incoming clock when calculating values of the output samples corresponding to time moments of the output clock. No ASRC can eliminate the effect of the incoming jitter completely, the time jitter will convert into value jitter.
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Typically the algorithms allow for changes in the input clock as well as output clock, continuously tracking their ratio. That's used e.g. by Henrik in his CamillaDSP where he adaptively resamples between independent clocks of the capturing and playback soundcards (even when running at different samplerates). Or ESS between any input I2S clock and the fixed master clock (or some fraction of it, e.g. MCLK/128).
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Yeah it's much simpler than this...
There's no PLL, it's an ASRC that operates between the oversampling filter and the sigma delta block. So it works at a very high sample rate, which makes it much simpler.
A normal SRC emulates oversampling, doing interpolation into the new sampling domain, then downsampling. ESS already had the oversampling block because it's a sigma delta DAC so it's got to have one, they removed the last step because there is no need for it, and I think the interpolation part is just good old linear interpolation.
I think I could do it, but then I do not have the exposure to broadcast the results, so...
Huh, an ES9311 (dual) is $4 and an OPA1612 (also dual) is $7. Think again the economics, if that's about.
ESS guarantees the data sheet performance for their DACs when using the ES9311 for AVCC. For an op amp buffer, you need a low noise LDO to feed the op amp anyway, since a single pole filter won't help much with filtering the input noise.
The ES9822 ADC uses ES9311 in the data sheet schematic (which is a pre-regulator, there is another low noise regulator on the chip).
There's another stage of IIR after the first 8x FIR stage. I don't remember its oversampling factor.
I am not planning to sell anything regarding this project (never did, BTW, life is too short to get into group buys, support, etc...) and budget is not a concern, at least not yet.
So I am planning to continue at my own pace, and update here with all the details (schematics, Gerbers when it will come to that, etc...). If someone would eventually like to use these for commercial purposes (something I do not encourage, in general), I'll see when it comes to that.
I certainly doubt there are many DIYAudio members here that have the tools and experience to assembly designs of this complexity. Except, of course, those that can design it themselves, anyway
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Let's see a back of napkin calculation. Your ADP151-3.3 has a datasheet typical noise on 9uV in 10-100KHz bandwidth (they call it "ultra low noise", well, it is not exactly so). You are using in the schematic posted in #970 an 56k/1uF filter, which has the 3dB roll of frequency response at about 18Hz. Meaning that it will provide a 20dB attenuation at 180Hz. We have to add to the op amp input noise sources the resistor itself, which is another 9.5uV in 10-100KHz bandwidth.
The total is about 60nV/rtHz, past the 180Hz filter you will get 0.8uV of noise. Which is as much as a LT3045 or ADM7154, or ES9311 will provide in the whole 10-100KHz bandwidth. Which one would be better?
To add insult to injury, you spent $1 for the ADP151 plus $7 for the OPA1612, while a ES9311 is $4.
P.S. A 5.6k/10uF filter would provide a net noise benefit, since the resistor noise power contribution would be 3 times lower.
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