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#461 |
diyAudio Member
Join Date: Oct 2003
Location: Europe-Asia
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Hi Doug, 2nd version was almost done as a prototype 2 years ago, but because of a other projects, we did not finished the full firmware tests. There a a lot of features and a lot of various operation modes combinations, which equired a lot of time to test.
BTW, I got many questions this year bout it. (Why this year? Why not 0.5y/1y or 1.5y ago? I don't know! Covid influence? ![]() So maybe I will force it now. |
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#462 |
diyAudio Member
Join Date: Sep 2005
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Alex I'd purchase one as soon as they are available. I'd love a remote (USB or ethernet) interface too...
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#463 |
diyAudio Member
Join Date: Oct 2003
Location: Europe-Asia
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I'll drop you a message.
Ethernet is too complicated, USB exists (USB2COM, isolated). |
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#464 |
diyAudio Member
Join Date: Aug 2005
Location: Toronto
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Can somebody tell from their own experience how much current is the ES9038PRO taking from:
+1.2V Analog (VDD_L, VDD_R) +3.3V Analog Reference (AVCC_L, AVCC_R) +1.2V Digital Core (DVDD) +3.3V Digital I/O (AVDD) +3.3V Oscillator (VCCA) I am confused by the numbers in the data sheet (attached). - Are these per channel (L/R) or the sum of currents on both channels? - Why are VDD_L, VDD_R and DVDD collapsed under the same value, are they assuming one will use the 1.2V supply to feed both the Analog and Digital Core sections. I read that the current value scale up (as expected) with the clock frequency, @100MHz and 768KHz is almost double the values @40MHz and 48KHz, anybody has any current consumption measurements @100MHz? |
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#465 |
diyAudio Member
Join Date: Jul 2016
Location: California
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ES9038PRO eval board appears to power DVDD, VDD_L, VDD_R all from the same regulator.
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#466 | |
diyAudio Member
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Quote:
Or I'm misunderstanding? |
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#467 |
diyAudio Member
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If you start at 0.1 Hz and stop integrating at 100 kHz, sure. Perhaps you should work on improving your phase noise above 100 Hz rather than digging for a post you can score a point against.
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#468 |
diyAudio Member
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You are both right. its all in how you measure jitter. And that can be a rabbithole since the connection between the different ways of looking at jitter : How to Measure Jitter << Microsemi. how those affect different signals in the output of a DAC (or input from an ADC) and how audible those effects are is still up for grabs. The only formal research I have seen suggests that this is all well under any audible threshold at least per AES: https://www.aes.org/tmpFiles/aessc/2...2id-2020-i.pdf
I'm always for making something better if you know how and it doesn't bring too many problems. But there are absurd limits (Sapphire whispering gallery source? High-power solid-state sapphire whispering gallery mode maser - PubMed). And be careful of looking at a single issue when there could be other related aspects that affect what you are pursuing.
__________________
Demian Martin Product Design Services |
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#469 | |
diyAudio Member
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Quote:
So according to your science what would be the correct integration bandwidth to calculate the jitter? 12kHz to 100MHz suitable for telecommunication? However you can also shift the integration bandwidth away from the carrier, the jitter will always be dominated by the phase noise closest to the carrier and not by the "flat" noise floor. Try using a phase noise to jitter converter. Lastly, the Pierce oscillator is followed by a couple of frequency doublers, so the noise floor inevitably increases. Although the jitter is almost one order of magnitude better. |
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#470 | |
diyAudio Member
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Quote:
I merely wrote "my instrument is broken" if "usually the LF part of the phase noise area has a rather small contribution", because my instrument measures the opposite. |
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