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Info for UltraAnalog Jitter Analyzer
Info for UltraAnalog Jitter Analyzer
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Old 14th July 2016, 09:14 PM   #21
1audio is offline 1audio  United States
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Info for UltraAnalog Jitter Analyzer
Quote:
Originally Posted by JohnW View Post
Measuring the MCLK input at the DAC / ADC is the critical point.

I suspect the Yokogawa jitter analyser will be rather limited in this application normally these type instruments have 50pS to 100pS time interval resolution. With a competent design Phase noise components should be less then a pS.
Unless its a ladder DAC. . . I have an HP 5370A with upgraded input and processor but its resolution is still really an order of magnitude too high. I don't think that is a path to useful info.

The PLL is also limited by both the PLL and the residual of the VCO (VCXO). To get good info on the phase noise of a Crystek or an NDK you really need a much more sophisticated solution, most likely one with cross correlation. Given that those are available for $30-$40 now it may be easier to just use one. When the phase noise is below a certain level its lost in the intrinsic noise and resolution of the DAC/ADC.

Here are some references for those who want to understand the jargon (I know John is up on this):
http://www.ieee-uffc.org/frequency-c...asurements.pdf
http://www.keysight.com/upload/cmc_u...?&cc=US&lc=eng
Low-Cost Phase Noise Measurement |
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Old 16th July 2016, 01:27 AM   #22
Murray Allen is offline Murray Allen  Canada
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Info for UltraAnalog Jitter Analyzer
Quote:
Originally Posted by JohnW View Post
Does anyone have a copy of Remy's Ultra Analog, Application Note AP-03:-

Jitter, Jitter, Jitter...
Fourre, Remy D.
Ultra Analog, Application Note AP-03
Here is the Ultra Analog application note AP-03
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File Type: pdf Jitter_AP-03.pdf (684.2 KB, 63 views)
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Old 22nd July 2016, 07:12 AM   #23
JohnW is offline JohnW  Hong Kong
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Murry,

Please forgive the delay, Thank you very much for the Scan of the Application note

Food for thought on the "comparative" Jitter analyser...

The unit I purchased is however the "PLL" type mentioned in the paper as "Ill suited to measurements of LF Phase noise" - well this design sure will be with the chosen capacitors used in the Integrator (and the input base current of the integrator Opamp)...
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Old 22nd July 2016, 07:30 AM   #24
Murray Allen is offline Murray Allen  Canada
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Info for UltraAnalog Jitter Analyzer
John,

I send you a PM with a link to the other article.

Murray
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Old 22nd July 2016, 08:01 AM   #25
kukynas is offline kukynas  Czech Republic
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Quote:
Originally Posted by JohnW View Post
Murry,

Thank you, the information is much appreciated - I can send you funds via PayPal to cover any costs if required.

I have a long term plan / dream to offer a budget jitter analyser for the DIY community - it will be an external "adaptor" that can interface with a ADC/DAC design with internal DSP I'm working on, but I guess can be used with any decent ADC and PC software.

Basically a phase noise (jitter analyser) system that should cost no more then US$200 to US$300 for fellow DIy'ers - I have a Agilent / HP phase noise Rack system in the corner of the lab I can use to calibrate and confirm performance:-

https://dl.dropboxusercontent.com/u/...tem%20Rack.JPG
that would be excellent, waiting for your progress even if I know you're busy with other stuff
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Old 14th August 2016, 08:35 PM   #26
stormsonic is offline stormsonic  Slovenia
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JohnW, you got private message
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Old 9th September 2019, 06:28 PM   #27
PSchut is offline PSchut  Netherlands
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Quote:
Originally Posted by Zero Cool View Post
A long time ago I acquired this UltraAnalog JA-B Jitter Analyzer. I can find ZERO Information on it. Does anyone recognize it? have any info on it? It may have been custom built. I have it listed FS on eBay but I have very little info about it.
Is this question still active.... sorry found this thread by accident.
I have the same analyzer, got it fro Ultra Analog when I did design work for them some 20 years ago.

It is a great device, I have the schematic somewhere (only on paper) and a schematic of the probe as well.

Cheers
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Old 10th September 2019, 06:54 AM   #28
JohnW is offline JohnW  Hong Kong
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Quote:
Originally Posted by PSchut View Post
Is this question still active.... sorry found this thread by accident.
I have the same analyzer, got it fro Ultra Analog when I did design work for them some 20 years ago.

It is a great device, I have the schematic somewhere (only on paper) and a schematic of the probe as well.

Cheers
I've got the unit sitting on top of a rack behind me - not had not much time to look at it, but I'd very much like to investigate the possibility of designing an affordable / DIY jitter analyzer for audio use.

I had a quick peak inside, but worried a bit when the probe interface which at first appears balanced, is in fact not.

The jitter detection Edge is chosen via an XOR (selected via the front panel edge switch).

I'd really appreciate the schematics, it might restart the project and I'd be happy to update the design for DIY users

DIY developers would really benefit from an affordable Jitter analyzer
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Old 11th September 2019, 08:31 AM   #29
HpW is offline HpW
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Quote:
Originally Posted by JohnW View Post
I've got the unit sitting on top of a rack behind me - not had not much time to look at it, but I'd very much like to investigate the possibility of designing an affordable / DIY jitter analyzer for audio use.

I had a quick peak inside, but worried a bit when the probe interface which at first appears balanced, is in fact not.

The jitter detection Edge is chosen via an XOR (selected via the front panel edge switch).

I'd really appreciate the schematics, it might restart the project and I'd be happy to update the design for DIY users

DIY developers would really benefit from an affordable Jitter analyzer
I have seen some Jitter Tool tests by the AP555 and looks as BS. Also only related using the SPDIF signal source and given result.

Also to provide for DIY users, this is a dream while it matters on HW & SW.

May read on the TI pdf, indicates that some jitter inherited to the DAC have to be done with additional signal injection to the clock.

https://training.ti.com/sites/defaul...nverters_3.pdf

hp
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