DIY programmable dual channel bench PSU 0-50V/3A

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Rise time...

LTspice model presented recently will produce for some reason not so attractive rise time for U_SET step function, tested with PWL(0 0 110u 0 120u 1 2.78m 1 2.8m 50m 3m 50m):

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In real life it looks much better/faster (115us!):

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  • Voltage step 0-20-0V, load=100R (LTspice).png
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  • Voltage step 0-20-0V, load=100R (tested).png
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Power board redesign...

From some previous posts became obvious that Power board which is hosting pre-regulator, post-regulator, bias powers and ADC/DAC sections will require massive redesign. New post-regulator is tested on breadboard and looks very promising. Also I made some testing with new power pre-regulator based on LM5088 device which makes a whole thing cheaper. Bias pre-regulator based on LM5574 works nice and will stay but for bias post-regulators I'd like to use more affordable items such as LM317, LM337 and LP2951.
I also starts to think that maybe splitting this board in two section will simplify a whole assembly and testing and make it a more flexible for the future modification when i.e. a modification on the pre-regulator side will not require to thrown away the post-regulator section.
This approach rise a new question: how to interconnect that two section that was previously reside on the same PCB? My first choice is to use board-to-board connectors such as Samtec HTSW-105-08-F-D-RA (Farnell: 1926980) and SSW-105-02-T-D-RA (Farnell: 2308470). A multiple pins will be used for power out and ground. According to Samtec power rating is at least 5.7A per pin. Actually I don't understand what does it mean: 1 pin powered per row in datasheet. Anyway I hope that four of them for power out will be more then enough for continuous 3A (or even 5A).
I'd like to ask you if you can suggest some better but still "down to Earth" solution.
 
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New model with improved OE circuit...

The model presented in post #39 include Output enable circuit which is not optimal. It has two issues: when active it drop Vout below zero (up to ~-0.45V) and when power is going down with OE activated some ugly artifacts appears on the output. Here is the measurement of the extreme case when no load is connected:

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The new model incorporate current mirror for controlling power mosfet bias and it resolves successfully before mentioned issues. Here is the schematics and .asc file is in the attachment. Note that if you have a problem with long calculation time for the whole model, simply remove CC/CV indicators section (down left).

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  • 2015-03-23 Post-regulator power down, OE disabled, no load.png
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  • New post-regulator model (2015-04-06).zip
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  • New post-regulator for PSU 0-50V (OE revised).png
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New power PCB...

Here is the latest revision of power pre-regulator and post-regulator with new PCBs where that two circuits are separated. Thanks to that I decide to play a little bit with pre-regulator and made two PCB: SMPS version based on LM5088 and another with p-ch mosfet driven by thyristor (will be presented in post that follow). Pre-regulator PCBs now also include floating charge pump to provide proper power mosfet bias on post-regulator board.
New power board is still comply with requirement that it can works without MCU (ADC, DAC and I/O expander are located on post-regulator PCB but are not mandatory for "manual" operation).

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  • Programmable PSU r3B36_1of11.png
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  • Programmable PSU 0-50V 3A diagram v2.png
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  • Programmable PSU r3B36 (top layer).png
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Mosfet pre-regulator PCB...

Mosfet pre-regulator is based on blackdog design presented here. It looks promising at least in spice simulation that is also attached.
Since I'm going to make a new power PCB I think that one is worth some effort and could be used at least for comparison with SMPS version.
 

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  • Blackdog pre-regulator.zip
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  • Mosfet pre-regulator r1B2 (all).png
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  • Mosfet pre-regulator r1B2 (bottom layer).png
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  • Mosfet pre-regulator r1B2 (top layer).png
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  • Mosfet pre-regulator v0.2_2of2.png
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  • Mosfet pre-regulator v0.2_1of2.png
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Floating charge pump for nmos gate bias

I'm adding here model of floating charge pump that I'm going to use in the latest revision of the PSU. It's intended to add on top of Vpreg voltage supplied from pre-regulator min. 5V to insure proper operation of power mosfet in the post-regulator. I made a basic testing on the breadboard and it seems that it works at least when DP (down-programmer) circuit is disabled: a whole gate driver that include OE (output enable) circuit in that case consume ~7mA. With DP enabled according to LTspice simulation another 5mA will be required. That is something that I currently cannot produce on breadboard - consumption goes crazy up to 55mA (!) which basic charge pump cannot deliver. If this problem persist possibly circuit presented in second model (555 charge pump v2 (booster).zip) could resolve this problem. This require further investigation.

Current charge pump float on top of the input voltage for the post-regulator (Vpreg). That is required since TLC555 circuit max. supply voltage is 18V. That is accomplished with D3, R3 and filtered with C4 and in that way set to max. 15V. R3 is a problem here if you'd like to cover a whole Vpreg range (2-52V). Even if its value is zero timer cannot work properly from 2V. Due to that auxiliary supply is added (+15V) which is already present in post-regulator circuit. The most critical range is when Vpreg is a little over 15V. If R3 is too high it will be too limiting, if it's too small it will dissipate to much heat. Chosen value of 1K2 is a compromise and in worst case (Vpreg=52V) it will dissipate ~1W.

Maybe R3 could be replaced with some active circuit to provide better limitation/regulation over the range of 15-52V. Any suggestion is welcome.

There is also another approach: to fix bias voltage to max. Vpreg (52V) + 5-12V and don't bother with mentioned auxiliary supply and issue when Vpreg is close to 15V.

The last possibility is to completely remove bias supply generated by charge pump. How that could be possible? If I use 48VAC on the input that rectified and filtered gives ~67VDC and put pre-regulator in-between which deliver 2-52V for the post-regulator it will act as some sort of "isolator" between Vin (67VDC) post-regulator where in the worst case (52V) difference for bias will be even in the case of max. load at least 12V.

To test mentioned scenarios I added some jumpers (JP2 and JP3 on Sheet 1) on the latest revision of the pre-regulator PCB.
 

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  • Charge pump v2.png
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  • charge pump v2 (results).png
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  • Charge pump v2.zip
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  • Charge pump v2 (booster).zip
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Charge pump revised

Here is another attempt to have a charge pump that can follow pre-regulator output voltage (Vpreg) and provide in the worst case 5V higher voltage as a power mosfet bias in the post-regulator. I didn't test it yet on the breadboard since I don't have DN2535 or similar depletion mosfet but circuit looks correct in LTspice. Simulated case shows how Vpreg changes from 5 to 32 and 52 and back to 5V. When Vpreg drops below 15V Vaux is used as a supply. According to this simulation Vaux could go down to 9V and that the 5V difference is preserved. DN2535 power dissipation is in the worst case ~1W that shouldn't be a problem to manage with tiny TO-220 clip-on heatsink.
 

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  • Charge pump v3.zip
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  • Charge pump v3 results.png
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PSU with Mosfet pre-regulator first results...

New PCBs arrived and I decided to start with testing blackdog's mosfet pre-regulator. It looks pretty good. It can deliver even with a single mosfet over 6A. With two of them it shouldn't be a problem to deliver declared 10A. I tested it with Vin=48VAC (67VDC) and single 10.000uF capacitor. I didn't measure capacitor current but according to spice model it goes far beyond what manufacturer declared as limit. A rise of its temperature can be detected but nothing alarming (so far).

As a post-regulator I used a new design based on Liv circuit and everything is tested strictly in CV mode. I found two issues: if Vin is mentioned 48VAC output enable circuit cannot bring Vout down to zero but to ~5V. If Vin is e.g. 40VAC it works perfectly. Another issue (or "it's a feature not bug" type of event) is possibly connected with pre-regulator: depends of Vout with the same load (16R4/100W resistor is used) transformer start buzzing. Mostly in the middle range (20-30V). See on the picture 2015-05-15 Mosfet pre-regulator, Vout=25V, Load=16R4.png how output from pre-regulator looks like in that case. Don't know is it normal that transformer is audiable with such type of output (it is completely silent with e.g. 2015-05-15 Mosfet pre-regulator, Vout=10V, Load=16R4.png or 2015-05-15 Mosfet pre-regulator, Vout=50V, Iout=3A.png shape of the output voltage).

I tried to measure overall efficiency of such combination of post-regulator board (r3B36) and blackdog's pre-regulator (r1B2). Cheap DMM has been used for measuring rms values so some significant error can be expected. But regardless of used instrument I noticed a considerable fluctuation in the middle range which I think is connected with transformer buzzing (and accompanied pre-regulator signal shape). Please find below results of three measurements (within 15 minutes time frame).
 

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  • Mosfet pre-regulator r1B2.JPG
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  • Mosfet pre-regulator r1B2 (2).JPG
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  • 2015-05-15 Mosfet pre-regulator, Vout=25V, Load=16R4.png
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  • 2015-05-15 Mosfet pre-regulator, Vout=50V, Iout=3A.png
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  • 2015-05-15 Mosfet pre-regulator, Vout=10V, Load=16R4.png
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  • PSU with mosfet pre-regulator efficiency graph.png
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  • PSU with mosfet pre-regulator efficiency data.png
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Mosfet pre-regulator board latest revision...

Few small changes are made on the mosfet pre-regulator board. Floating charge pump is removed since post-regulator works in full range, full load (0-50V, 3A and up to 5A!) with Vin=48VAC without it. The most important thing is adding of D3 to isolate C3 from mosfet input since witout that it will be in a real trouble trying to deliver something what is not intended :). Also sync isolator is added when more SMPS is presented (like in dual channel version or when MCU board is deployed). The latest schematic is attached.
 

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  • Mosfet pre-regulator r2B4_1of2.png
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  • Mosfet pre-regulator r2B4_2of2.png
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Small update

if Vin is mentioned 48VAC output enable circuit cannot bring Vout down to zero but to ~5V. If Vin is e.g. 40VAC it works perfectly.
I fixed this one by changing BC557B in OE (output enable) current mirror with BC640. Actually with Vin=48VAC emitter-collector voltage goes beyond BC557B's allowed maximum (if max. Vceo=50V). With BC640 that limit is rised to 80V.
 
Mosfet pre-regulator update...

I made a progress with pre-regulator issue described here. C2 capacitor of 1nF was too big and it's replaced with 560pF. Now that switching frequency drop from 100Hz to 50Hz in the middle range is not happened any more. Thanks to that efficiency curve is now linear.
Used LTspice model didn't show that with 1nF (560pF in practice) but it can be pushed in that mode of operation with i.e. 2nF (1nF in practice). A new model, real and simulated results are in attachment. You can also see a difference in dissipated power on mosfet with different timing.
Presented measurements are for Vout=5, 30 and 50V.
 

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  • Mosfet pre-regulator model.zip
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  • Mosfet pre-regulator simulation (2nF).png
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  • Mosfet pre-regulator simulation (1nF).png
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  • 2015-05-27 Pre-regulator timing, Vout=50V, load=16R4, C=560pF.png
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  • 2015-05-27 Pre-regulator timing, Vout=30V, load=16R4, C=560pF.png
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  • 2015-05-27 Pre-regulator timing, Vout=5V, load=16R4, C=560pF.png
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  • PSU with mosfet pre-regulator efficiency (560pF).png
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Power down without load and bad timing...

I'd like to present here what's happening during power down with Vout set below ~12V and no load is connected. Vout shortly after power down goes crazy peaking 11.7V. That is not the case if some load is connected but regardless of that it looks bad and need to be fixed. The source of the problem was PWRGOOD signal that is used to shut down (using OE circuit) output and is derived from the wrong place, namely +5V LDO. Since that LDO has a much more room to deliver regulated output then +15V (Vdd) LDO it's logical that PWRGOOD signal will lasts too long. On the other side Vdd which is used to supply CV control loop drops too fast and lost control over the loop.
Unfortunately on the current PCB a LM317 is deployed for +15V which do not have any power monitoring. Therefore in a new PCB revision an another type of LDO or discrete PWRGOOD logic has to be added. Maybe the easiest way is to deploy another LP2951 as in the case of +5V which is cheap and could deliver up to 100mA what is more then enough.
 

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  • 2015-05-22 Post-regulator Vout, no load, Vset=5V, wrong power down sequence.png
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Huge trouble with "Ebay grade" panel meters...

I had a tough time trying to figure out why output signal looks horrible when post-regulator enters CC mode (see first two picture). The first suspect was PCB. I'm not happy with current revision since due to urge to put so much components in so little space it ends up with having e.g. far from optimal ground plane. Also in the designing process I completely forgot to dedicate separate track to supply current shunt resistor. But even if I failed miserably (what actually is not a case) I was wondering why even with the smallest current PSU in CC mode behave in such way. I tried to accuse some other part of the post-regulator, but without real reason since it works nicely while in the CV mode.
I started to populate another post-regulator PCB this time with CC loop components only. That combination didn't work (you'll see soon why). I then went to breadboard and there it works! I even try to test everything on bare PCB with current shunt monitor op amp (LTC2057) and minimum surrounding components. That generate even more confusion since in that case it works without changing the rest. But that was not completely true. I didn't connect load to DMM's ammeter but connect it directly to the "high side" of shunt resistor. I didn't spot that at once and after many attempts I finally today realize that eBay grade panel DMM is connected with that noise generation!
I have two different version, and yes, they are really different: each has its own "noise signature" :). I don't know why they behave like that. Maybe the problem is a combination with PSU which has "low side" current monitoring but this issue really made me in one moment miserable. I started to think about various other op amp hoping that LTC2057 is not appropriate for such "lame" PCB and that with some other less sensitive this issue will disappear. I even start to think about another PCB revision (too soon since the next one should be in proper condition that can generate a group buy and Eagle and Gerber files can be publish).
I was thinking that first milestone will be a PSU which is fully functional with manual controls only, but it seems that I need to continue with adding MCU board or eventually (to say that milestone is reached) to find out why combination with such DMMs does not work (or maybe find some other which works fine and does not cost another fortune).
I'm wondering if anybody else has similar experience?
 

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  • 2015-05-28 Vout noise with DMM type II.png
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  • 2015-05-28 Vout noise with DMM type I.png
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  • LTC2057HV breadboard.jpg
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  • 2015-05-11 Post-regulator CC loop only.JPG
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  • Shunt monitor on separate PCB.JPG
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Hello prasimix,

As soon you start to design power supply in switching mode, routing and ground path are much more critical and EMI issue occur easily.
IMHO, routing your design in only two layers is bad idea. Of course two layers is cheaper than four, but with two layers it's impossible to get a massive uncut ground plane. I don't have analyze in depth your design, but it's possible that some of your issue comes from that.
Otherwise your project is ambitious and will learn you many thing when it will be finished !
Regards.

Frex
 
Hello prasimix,

As soon you start to design power supply in switching mode, routing and ground path are much more critical and EMI issue occur easily.
IMHO, routing your design in only two layers is bad idea. Of course two layers is cheaper than four, but with two layers it's impossible to get a massive uncut ground plane. I don't have analyze in depth your design, but it's possible that some of your issue comes from that.
Otherwise your project is ambitious and will learn you many thing when it will be finished !
Regards.

Frex

Thanks Frex for your input. Four layers sounds fine but I cannot afford it and hopefully will succeed to do everything properly with just two. Maybe switch from THT to SMT could improve situation but I still don't have experience with such approach and don't know if such move can helps in designing better PCB or makes a whole thing a mission impossible on two layer with level of complexity presents in chosen PSU circuit.
Anyway I'm happy that I resolve a mystery (and misery) caused with that DMMs since now I can continue with testing and tweaking.
 
Re: Power down without load and bad timing...

This is a follow up to post #52 where I announced that PWRGOOD signal has to be moved from +5V to +15V LDO. That is actually not enough what is clearly visible on the following picture:

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Improvement is visible since Vout (set to 3.3V) overshoot without load is now smaller and last less time but it's still there and it's actually massive (yellow trace). It's connected with lack of ULVO (Undervoltage-lockout) control of bias pre-regulator (LM5574). It try to insure propoper voltage all the time but cannot manage that (since is is not buck/boost but only buck) when Vin drops below ~35V. That cause oscillation of the output what is reflected to the PWRGOOD signal. With adding ULVO (voltage divider 51K/1K5 to disable output when Vin drops to ~43VDC everything looks fine as you can see on the following picture:

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One thing less on TO-DO list :). I now have a pretty complete "non-SMPS power" pre-regulator board where I decide to add one more thing that I'll describe in one of future posts.
 

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  • 2015-06-01 PSU power up sequence PWRGOOD signal on +15V LP2951 + ULVO on LM5574 (2).png
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  • 2015-06-01 PSU power up sequence PWRGOOD signal on +15V LP2951.png
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Testing capacitive load, part I

In the few posts thats follow I'd like to present how PSU (with mosfet pre-regulator) behave when huge capacitive load is connected with or without additional resistive load. I tested it with 470, 1000, 2200 and 10000uF.
Also you can see a benefits of DP ("down-programmer").

First let see what happened with 470uF connected to Vout (step is created using OE control) with and without DP activated (default is on). You can see that without DP due to capacitor discharge Vout require tens of seconds to reach zero volt after OE (Output enable) is set off.
 

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  • 2015-05-30 PSU OE on, Vout=50V, load=470uF, DP on.png
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  • 2015-05-30 PSU OE on, Vout=50V, load=470uF, DP off.png
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Testing capacitive load, part II

The following pictures presents how PSU behave with 1000, 2200 and 10000uf when Vout is set to 50V. I also tried 4x4.7uF ceramic to test if extremely low ESR will cause oscillation. In all cases DP was on, and you can see that it requires some time to discharge capacitor since it use 2R2 to do it. For 10000uf that lasts ~1sec.
 

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  • 2015-05-30 PSU OE on, Vout=50V, load=10000uF, DP on.png
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  • 2015-05-30 PSU OE on, Vout=50V, load=2200uF, DP on.png
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  • 2015-05-30 PSU OE on, Vout=50V, load=1000uF, DP on.png
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  • 2015-05-30 PSU OE on, Vout=50V, load=4x4.7uF, DP on.png
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Testing capacitive load, part III

Now we comes to more interesting part where additional load is connected what is closer to real scenario when D.U.T. (Device under test) is connected to the PSU. Here we are reaching some limits of what PSU in this revision can do, but I think that it still pretty good and better then average.
This is a also example how DP can improve situation. I tested 1000uF with 16R4 load in parallel on 25V and 40V which alone consume 1.5A and 2.4A. That means that when Vout appears on output terminals that for charging capacitor remain 1.65 or only 0.75A before PSU enters CC mode. Regardless of that when DP is on it can handle both cases nicely. But if DP is set off then you can see oscillation.
If smaller load is connected (33R instead of 16R4) that gives more room for handling capacitor charging and in that case it can go up to maximum 50V. Of course with DP set on. If DP is switched off you can expect oscillation. Of course someone could interpret using od DP as cheating, but I see it as a nice feature.
As mentioned before even with DP PSU has some limitation, that is finite current that it can deliver and that is controlled with CC loop and set it this case to 3.15A. You can see that in the latest picture (50V, load=1000uF+16R4).
All mentioned is my interpretation of presented results and it's possible that it not correct, so your inputs as usual is more then welcome.
 

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  • 2015-05-30 PSU OE on, Vset=50V, load=1000uF+16R4, DP on (oscillation!).png
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  • 2015-05-30 PSU OE on, Vout=50V, load=1000uF+33R, DP off (osciallation!).png
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  • 2015-05-30 PSU OE on, Vout=50V, load=1000uF+33R, DP on.png
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  • 2015-05-30 PSU OE on, Vout=25V, load=1000uF+16R4, DP off (oscillation!).png
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  • 2015-05-30 PSU OE on, Vout=40V, load=1000uF+16R4, DP on.png
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  • 2015-05-30 PSU OE on, Vout=25V, load=1000uF+16R4, DP on.png
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Testing capacitive load, part IV

I found yesterday that PSU can perform much better. C63 in current error amplifier feedback (see post #44) was too small. When I increased it to 1nF with current set (I_SET) to maximum (3.15A) it manage nicely 16R4 in parallel with 10000uF on max Vout (50V). I can easily go over it: Second picture is 16R4 || 20000uF combination on max Vout.
 

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  • 2015-06-03 PSU OE on, Vout=50V, load=10000uF+16R4, DP on.png
    2015-06-03 PSU OE on, Vout=50V, load=10000uF+16R4, DP on.png
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  • 2015-06-03 PSU OE on, Vout=50V, load=20000uF+16R4, DP on.png
    2015-06-03 PSU OE on, Vout=50V, load=20000uF+16R4, DP on.png
    33.9 KB · Views: 63
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