Hello. For quite some time I've been tossing around idea of analog linear interpolation during the DAC IV stage. So I hope to get your comments to this very idea. Note that I haven't built any such thing. I have only simulated results. But they look interesting.
Linear analog interpolation - putting slew rate limiting to good use.
Normal DAC outputs step current that is then feeded into IV conversion circuit that produces step Voltage proportional to PCM sample values. This step voltage is then filtered to remove garbage inherent to the steps. The steps themselves offer very difficult signal for linear circuits.
What is proposed here is method of implementing DAC with linear interpolation in analog domain which effectively completely limits the slew rate of the signal to easily manageable levels.
To grasp the approach consider how linearily interpolated samples are calculated - interpolated sample is average of two subsequent real samples, exactly halfway on the time axis. If you continue adding interpolated values between newly calculated values, you get straight line between real sample values.
That straight line can be represented as slew rate (Volts/sec) required to reach next real sample value after finite sampling interval expires. In essence, stream of PCM data can be easily converted into list of slew rate values that alternate in sign and value at each sampling interval.
Now, constant current source feeding into capacitor will produce monotonously increasing voltage on the capacitor, and basically slew rate of that voltage is proportional to applied current. Given any capacitor value, stream of slew rate values converted into proportional current when applied to capacitor will produce signal that exactly corresponds to PCM sample values with infinite number of linearily interpolated intermediate values. see dac77.gif
To produce suitable stream of current values to be applied to IV capacitor, it is required during each sampling interval to produce current that is proportional to difference between recent sample and previous sample. Then, such delta current is proportional to the required slew rate and signal on capacitor linearily approaches analog value of the next PCM sample at time instant of next sampling interval.
The easiest way to generate suitable delta current stream is to use 2 channels of a stereo DAC with current outputs, and delay input PCM data for 1 sample interval before feeding second channel of this DAC. Then, difference of outputs of the 2 channels will be delta current and our slew rate stream. The 2 outputs can be substracted, (e.g. by connecting out- with out+ of other channel), and the resultant delta current fed into IV capacitor.
Voltage on the IV capactitor will be precisely proportional to PCM data at infinitesimal instants between consecutive samples, but instead of steps there would be linear voltage increase between sample values. Amplitude of the resultant output voltage will be dependant on capacitor absolute value, larger capacitor will produce lower amplitude output, by means of limiting maximum possible slew rate between sampling intervals. see dac6.gif
Benefits of such DAC IV conversion.
1 - maximum possible slew rate of the IV output is best controlled, no matter what PCM input.
2 - there is effectively infinite number of interpolated intermediate samples - like infinite OS.
3 - output of such IV is easy signal to filtering and amplification.
4 - step signal is replaced by triangular signal which contains less harmonics than rectangular signal, these harmonics have less energy and roll off faster.
5 - for PCM signals approaching lower frequency limit triangular signal is increasingly approaching exact representation of the analog sinewave with very little upper harmonics. For e.g. sinewave with frequency FS/20 has inband harmonics below -130db and aliases -60db before any filtering.
6 - aliasing harmonics are more than 20db below what step signal produces - ie. simpler filter.
7 - impulse response is as ideal as it can get.
8 - IV converter settling time is a moot - there is NO settling time of IV as such, its a linear system.
9 - settling time errors of DAC do not cause voltage spikes - they are limited by max slew rate on IV capacitor.
10 - Coupled with DSP sinc interpolation and oversampling, could allow DAC without antialiasing filter at all.
11 - most nonlinearity is located at sinewave peaks. Region of zero transit is most linear.
Downsides.
1 - there is inherent roll off of about 4-6db at highest inband frequencies due to output signal approaching pure triangular wave and that contains less area (energy) than step signal has.
2 - linear interpolation is academically unable to precisely reconstruct original sinewave if compared to hypothetical ideal brickwall filter applied to step signal. There is unavoidable error signal present, and it increases in magnitude with increasing inband frequency. This manifests as roll off in higher band and as harmonics beyond signal band. Basically difference between linear and sinc interpolation. But sonics of this is unknown. I personally think linearity of lower band is more important.
3 - output voltage is floating. As this is basically delta modulation, output signal zero is not strictly fixed, but depends on previous PCM data. This can be a problem, as asymetrically clipped PCM signal can cause DC output buildup. DC can be filtered out, main issue is with IV capacitor which drifts towards power rails. Some sort of soft DC servo seems unavoidable here.
4 - very sensitive to jitter.
what else?
Linear analog interpolation - putting slew rate limiting to good use.
Normal DAC outputs step current that is then feeded into IV conversion circuit that produces step Voltage proportional to PCM sample values. This step voltage is then filtered to remove garbage inherent to the steps. The steps themselves offer very difficult signal for linear circuits.
What is proposed here is method of implementing DAC with linear interpolation in analog domain which effectively completely limits the slew rate of the signal to easily manageable levels.
To grasp the approach consider how linearily interpolated samples are calculated - interpolated sample is average of two subsequent real samples, exactly halfway on the time axis. If you continue adding interpolated values between newly calculated values, you get straight line between real sample values.
That straight line can be represented as slew rate (Volts/sec) required to reach next real sample value after finite sampling interval expires. In essence, stream of PCM data can be easily converted into list of slew rate values that alternate in sign and value at each sampling interval.
Now, constant current source feeding into capacitor will produce monotonously increasing voltage on the capacitor, and basically slew rate of that voltage is proportional to applied current. Given any capacitor value, stream of slew rate values converted into proportional current when applied to capacitor will produce signal that exactly corresponds to PCM sample values with infinite number of linearily interpolated intermediate values. see dac77.gif
To produce suitable stream of current values to be applied to IV capacitor, it is required during each sampling interval to produce current that is proportional to difference between recent sample and previous sample. Then, such delta current is proportional to the required slew rate and signal on capacitor linearily approaches analog value of the next PCM sample at time instant of next sampling interval.
The easiest way to generate suitable delta current stream is to use 2 channels of a stereo DAC with current outputs, and delay input PCM data for 1 sample interval before feeding second channel of this DAC. Then, difference of outputs of the 2 channels will be delta current and our slew rate stream. The 2 outputs can be substracted, (e.g. by connecting out- with out+ of other channel), and the resultant delta current fed into IV capacitor.
Voltage on the IV capactitor will be precisely proportional to PCM data at infinitesimal instants between consecutive samples, but instead of steps there would be linear voltage increase between sample values. Amplitude of the resultant output voltage will be dependant on capacitor absolute value, larger capacitor will produce lower amplitude output, by means of limiting maximum possible slew rate between sampling intervals. see dac6.gif
Benefits of such DAC IV conversion.
1 - maximum possible slew rate of the IV output is best controlled, no matter what PCM input.
2 - there is effectively infinite number of interpolated intermediate samples - like infinite OS.
3 - output of such IV is easy signal to filtering and amplification.
4 - step signal is replaced by triangular signal which contains less harmonics than rectangular signal, these harmonics have less energy and roll off faster.
5 - for PCM signals approaching lower frequency limit triangular signal is increasingly approaching exact representation of the analog sinewave with very little upper harmonics. For e.g. sinewave with frequency FS/20 has inband harmonics below -130db and aliases -60db before any filtering.
6 - aliasing harmonics are more than 20db below what step signal produces - ie. simpler filter.
7 - impulse response is as ideal as it can get.
8 - IV converter settling time is a moot - there is NO settling time of IV as such, its a linear system.
9 - settling time errors of DAC do not cause voltage spikes - they are limited by max slew rate on IV capacitor.
10 - Coupled with DSP sinc interpolation and oversampling, could allow DAC without antialiasing filter at all.
11 - most nonlinearity is located at sinewave peaks. Region of zero transit is most linear.
Downsides.
1 - there is inherent roll off of about 4-6db at highest inband frequencies due to output signal approaching pure triangular wave and that contains less area (energy) than step signal has.
2 - linear interpolation is academically unable to precisely reconstruct original sinewave if compared to hypothetical ideal brickwall filter applied to step signal. There is unavoidable error signal present, and it increases in magnitude with increasing inband frequency. This manifests as roll off in higher band and as harmonics beyond signal band. Basically difference between linear and sinc interpolation. But sonics of this is unknown. I personally think linearity of lower band is more important.
3 - output voltage is floating. As this is basically delta modulation, output signal zero is not strictly fixed, but depends on previous PCM data. This can be a problem, as asymetrically clipped PCM signal can cause DC output buildup. DC can be filtered out, main issue is with IV capacitor which drifts towards power rails. Some sort of soft DC servo seems unavoidable here.
4 - very sensitive to jitter.
what else?
Attachments
This is one of the most innovative ideas I've seen on this forum in a long time! Lot's of outside-the-box thinking here!
I think downsides 1 and 2 are not as bad as it seems. They only apply if you use non-os dac's, and even then it is not worse than regular non-os dac.
Downside 4 needs some explanation, why is this worse than normal dac wrt. jitter?
Additionally it has the same downside as using a resistor for I/V in that you will not have a virtual ground at the dac output.
The delay can be implemented with a fifo-chip like TI 74ALC2226, a cpld or a bunch of 8-bit registers.
Did you have a specific dac-chip in mind? Also a conceptual schematic would be informative
Keep up the good work!
I think downsides 1 and 2 are not as bad as it seems. They only apply if you use non-os dac's, and even then it is not worse than regular non-os dac.
Downside 4 needs some explanation, why is this worse than normal dac wrt. jitter?
Additionally it has the same downside as using a resistor for I/V in that you will not have a virtual ground at the dac output.
The delay can be implemented with a fifo-chip like TI 74ALC2226, a cpld or a bunch of 8-bit registers.
Did you have a specific dac-chip in mind? Also a conceptual schematic would be informative
Keep up the good work!
How about if you just shove the stepped samples from a single DAC into an opamp integrator? If the DAC is a current output type the opamp can function as the I to V stage as well.wimms said:
Edit -> Just had a think about this; my idea is not the same thing at all but I understand *exactly* what you are aiming for. Gotta think some more about this...
When step DAC instantaneous jitter causes full sample-time error (just imagine one extreme), then max error is not directly amplitude error, but appears only after filtering. When delta current misses full sample, amplitude can swing fully peak-to-peak. Thats notable difference. Thats how I understand it.ojg said:
Amplitude errors of step DAC are constrained by absolute levels of DAC output, while in delta mode these errors can cumulate without limits.
Virtual ground can be maintained if low input impedance current amp is used.
Jocko, op-amps or their abilities was not my concern, especially not as an I/V. Central idea is linear interpolation. Mainly because its doable. Now my only concern is if its useful. And, in relative terms, its easier signal to anything after IV.Jocko Homo said:
Circlotron, one of points in doing it so is the relative simplicity of current summing, its almost passive nature. Integrator on normal DAC will not get you there. But you could generate delta current PCM data in DSP (e.g. PC) and then feed integrator. Well, it would be pretty much multibit DSD then.
You stated a potential implementation as two DACS slightly out of step in time (1 sample). Would not gain differences and other non-linearities between the DACS make this impossible from an implementation standpoint. With sigma-delta DACs you will at least get good low level linearity, however, if you use a linear PCM DAC, the bit - bit differences between the two DACS would negate the advantages I would expect. What I foresee is a loss of low level linearity and resolution.
I have to give some thought to that 4-6db roll off. When I was thinking of what you were saying, it sounded like you would essentially be implementing a first order filter (mathematically speaking).
Interesting though.. would be interesting to see how the implementation comes.
Alvaius
I have to give some thought to that 4-6db roll off. When I was thinking of what you were saying, it sounded like you would essentially be implementing a first order filter (mathematically speaking).
Interesting though.. would be interesting to see how the implementation comes.
Alvaius
Righto then, here we go! This will enable anyone to relatively easily try out the idea.
1/ Get a *mono* wav file of whatever you want to listen to.
2/ Open it with CoolEdit and save it as an ASCII txt file.
3/ Process this txt file with the attached "difrence.exe" file
4/ Load the resulting txt file with CoolEdit and save as a wav file.
5/ Use this wav file to burn a normal audio CD.
6/ The voltage samples from your DAC are now the *difference* values of adjacent samples - Use these samples to drive a plain old op-amp integrator. The integrator output will be "join-the-dots" provided a suitable R&C value is chosen.
The DC gain of the integrator will have to be rolled off though otherwise it's output will eventually drift over to one rail or the other.
Example of CoolEdit txt audio file below:
SAMPLES: 455346
BITSPERSAMPLE: 16
CHANNELS: 1
SAMPLERATE: 22050
NORMALIZED: FALSE
954
-164
-681
-111
1147
2295
2542
2540
2892
3544
3990
etc etc
Have fun!
P.S. the difrence.exe file has to do a lot of work so it is a little slow; start with a small file first!
1/ Get a *mono* wav file of whatever you want to listen to.
2/ Open it with CoolEdit and save it as an ASCII txt file.
3/ Process this txt file with the attached "difrence.exe" file
4/ Load the resulting txt file with CoolEdit and save as a wav file.
5/ Use this wav file to burn a normal audio CD.
6/ The voltage samples from your DAC are now the *difference* values of adjacent samples - Use these samples to drive a plain old op-amp integrator. The integrator output will be "join-the-dots" provided a suitable R&C value is chosen.
The DC gain of the integrator will have to be rolled off though otherwise it's output will eventually drift over to one rail or the other.
Example of CoolEdit txt audio file below:
SAMPLES: 455346
BITSPERSAMPLE: 16
CHANNELS: 1
SAMPLERATE: 22050
NORMALIZED: FALSE
954
-164
-681
-111
1147
2295
2542
2540
2892
3544
3990
etc etc
Have fun!
P.S. the difrence.exe file has to do a lot of work so it is a little slow; start with a small file first!
Back to the post:
thought of this long ago too. Why? because i read a folder about the harman/kardon RLS players:
Quote:
RLS process: injecting a preview of the dig audio signal ahead of the main signal. A blending device called an integrating comparator superimposes the first advanced signal over the second one, resulting in a smoothing of the stepped dig signal.
In effect RLS connects the stairs represented by the data points of each bit of dig music... Technally speaking, RLS is making a lin interpolation between two consecutive samples....
end Quote
They use a onepole low pass with -3dB @ 88kHz, discrete analog outputs with low neg feedback. Convertors are PCM61P, four of them, 8x oversampling. HD7725,7625,7527 are the types, from 1993. Remember the mags found them a bit 'soft'.
Now how to 'translate' the above into a schematic? The above text implies the use of an integrator, but then why 2 dacs/channel?
Interesting to continue here, happen to have a dac with two current dacs with one dac 1 sample after the other (45xx 64bit shift register). Now using i/v resistors and a transformer to add them up (~2xOS). Would not mind experimenting a bit.
thought of this long ago too. Why? because i read a folder about the harman/kardon RLS players:
Quote:
RLS process: injecting a preview of the dig audio signal ahead of the main signal. A blending device called an integrating comparator superimposes the first advanced signal over the second one, resulting in a smoothing of the stepped dig signal.
In effect RLS connects the stairs represented by the data points of each bit of dig music... Technally speaking, RLS is making a lin interpolation between two consecutive samples....
end Quote
They use a onepole low pass with -3dB @ 88kHz, discrete analog outputs with low neg feedback. Convertors are PCM61P, four of them, 8x oversampling. HD7725,7625,7527 are the types, from 1993. Remember the mags found them a bit 'soft'.
Now how to 'translate' the above into a schematic? The above text implies the use of an integrator, but then why 2 dacs/channel?
Interesting to continue here, happen to have a dac with two current dacs with one dac 1 sample after the other (45xx 64bit shift register). Now using i/v resistors and a transformer to add them up (~2xOS). Would not mind experimenting a bit.
wimms,
If you are proposing linear interpolation,then for a stream of samples A,B,C,D, you produce an output stream such that the output is A, (A+B)/2, B, (B+C)/2, C, (C+D)/2, D and you end up with twice the number of samples you started with. You can either sum these digitally, in which case the dac needs to work twice as fast and needs a greater wordlength or you can use two dacs working alternately with the outputs summed. Nothing unusual here and this has been done before all the way up to 64 dacs in parallel but there is no easing of the slew rate requirements.
However the gist of your post suggests something more akin to a one-bit dac but you refer to a difference between a sample and a delayed version of its self and in that case there can be no difference.
So what exactly are you proposing?
If you are proposing linear interpolation,then for a stream of samples A,B,C,D, you produce an output stream such that the output is A, (A+B)/2, B, (B+C)/2, C, (C+D)/2, D and you end up with twice the number of samples you started with. You can either sum these digitally, in which case the dac needs to work twice as fast and needs a greater wordlength or you can use two dacs working alternately with the outputs summed. Nothing unusual here and this has been done before all the way up to 64 dacs in parallel but there is no easing of the slew rate requirements.
However the gist of your post suggests something more akin to a one-bit dac but you refer to a difference between a sample and a delayed version of its self and in that case there can be no difference.
So what exactly are you proposing?
- Status
- This old topic is closed. If you want to reopen this topic, contact a moderator using the "Report Post" button.