I have a digital audio source with I2S output varying between 48kHz / 96kHz and 192kHz (and similarly for the 44.1kHz family as well), from which I would like to have an output sampling rate of 192kHz (or 176.4kHz) in all cases.
I have an idea that uses a variable oversampling factor for SCLK and variable division ratio for bit-clock (BCLK) according to the sampling frequency (below). Please tell me if it would work and correct me if I'm wrong.
Fs | LRCLK | BCLK (24-bits) | SCLK
48k | 48k | 64x48k | 256x48k. (oversampling = 256x and SCLK / BCLK divider = 4)
96k | 96k | 64x96k | 128x96k. (oversampling = 128x and SCLK / BCLK divider = 2)
192k | 192k | 64x192k | 64x192k. (oversampling = 64x and SCLK / BCLK divider = 1)
Besides, could the above method lead to any serious disadvantages (if it works) when compared to 2x/4x upsampling blocks?
Thanks in advance.
I have an idea that uses a variable oversampling factor for SCLK and variable division ratio for bit-clock (BCLK) according to the sampling frequency (below). Please tell me if it would work and correct me if I'm wrong.
Fs | LRCLK | BCLK (24-bits) | SCLK
48k | 48k | 64x48k | 256x48k. (oversampling = 256x and SCLK / BCLK divider = 4)
96k | 96k | 64x96k | 128x96k. (oversampling = 128x and SCLK / BCLK divider = 2)
192k | 192k | 64x192k | 64x192k. (oversampling = 64x and SCLK / BCLK divider = 1)
Besides, could the above method lead to any serious disadvantages (if it works) when compared to 2x/4x upsampling blocks?
Thanks in advance.
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Hi Lampie,
Thanks, I understand that many of you audiophiles use such boxes to get high quality interpolation, but I am not however, looking for the most accurate method available. I just want to increase the data rate in order to avoid the necessity to recalculate all the processing after any sampling frequency changes.
Regards.
Thanks, I understand that many of you audiophiles use such boxes to get high quality interpolation, but I am not however, looking for the most accurate method available. I just want to increase the data rate in order to avoid the necessity to recalculate all the processing after any sampling frequency changes.
Regards.
If they think a 100ms delay for lipsync is ok I wonder what other stupidity they think is ok. And there "tech specs" are useless.
I would use it only for music playback (no video). The specs are indeed totally worthless as is their website!
You do not need to take my word for it but it is a step in the right direction in digital filter design even it can not be found in the specs.
So if you have chance to try it please do so.
You do not need to take my word for it but it is a step in the right direction in digital filter design even it can not be found in the specs.
So if you have chance to try it please do so.
If you want to do it in hardware, at good ASRC (e.g. SRC4392 or AK4137) on a well-implemented PCB can serve quite nicely, very close to synchronous upsampling.
Alternatively, if you want fully synchronous upsampling, a DSP chip or FPGA can be programmed to do it.
Also, it can be done synchronously in in software.
Otherwise, if you want to understand how upsampling works in the digital domain, it doesn't work the way you seem to be suggesting. One can't simply change clock rates and get correct results. The data has to be interpolated and filtered as well.
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Thank you for your responses.
If this output came from a codec chip, then wouldn't it satisfy all these requirements? That is, the sampling frequency would be known for which the oversampling ratio could accordingly be set (PLL is software). Further, as the BitCLK and LRCLK for the data are directly obtained from the SCLK using dividers, the data is already synchronous to it. Does that make things any better?
I am not very good with bit-streams, I2S etc., and could therefore make really silly mistakes that the more experienced people could clearly see through and (possibly) correct. That was why I asked this question in the first place. Besides, I'm sure there are many people like me, looking to get a uniform data rate for all their content, as it makes things like processing etc. practically simpler. Thanks again.
Synchronous means there is one master clock for the whole system, for everything. If that can be assured, which in some cases it can, then synchronous is possible.
For example, what is called 'asynchronous USB' is actually synchronous with the dac clock, and asynchronous with the computer clock sending the USB data. For something SPDIF, a FIFO buffer (such as iancanada's FIFO_Pi) can be used.
'Synchronous' does not apply to two independent clocks of nominally the same frequency.
An example of synchronous upsampling with sensing of input sample rate can be found in another thread: Simple DSD modulator for dsc2 ...Although they also convert the upsampled output to DSD.
For example, what is called 'asynchronous USB' is actually synchronous with the dac clock, and asynchronous with the computer clock sending the USB data. For something SPDIF, a FIFO buffer (such as iancanada's FIFO_Pi) can be used.
'Synchronous' does not apply to two independent clocks of nominally the same frequency.
An example of synchronous upsampling with sensing of input sample rate can be found in another thread: Simple DSD modulator for dsc2 ...Although they also convert the upsampled output to DSD.
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I seem to understand somewhat better now, I think. Increasing the bit-clock would only repeat the bits but what we need to do is repeat the whole sample (all 24 bits), which means that we have to wait until the end of the sampling period (32/fs) to get all the bits for the sample and then carry out the repetition.
According to what I originally meant, if an 8-bit sequence is 10101010 (= 170), the 2x result would be 1100110011001100 (= 204, twice) which is a totally different number because of its messed up place values, arising out of repeated bits. However, if it's the whole sample that is being repeated, then the result must be 1010101010101010, which is same as 170 occurring twice.
I get my mistake. Nevertheless, repeating entire samples does result in (non-interpolated) upsampling, that has a similar (but narrower) frequency spectrum.
EDIT: I understand 'synchronous' as being of the same phase. For example, the final 1Hz clock of a digital watch is synchronous to the 32.768kHz crystal oscillator it's made from, by way of a 15-bit (1/32768) divider. In essence, there is this one clock from which all the others come, no matter the division ratio. This is usually the HDMI / SPDIF clock if I understand correctly.
According to what I originally meant, if an 8-bit sequence is 10101010 (= 170), the 2x result would be 1100110011001100 (= 204, twice) which is a totally different number because of its messed up place values, arising out of repeated bits. However, if it's the whole sample that is being repeated, then the result must be 1010101010101010, which is same as 170 occurring twice.
I get my mistake. Nevertheless, repeating entire samples does result in (non-interpolated) upsampling, that has a similar (but narrower) frequency spectrum.
EDIT: I understand 'synchronous' as being of the same phase. For example, the final 1Hz clock of a digital watch is synchronous to the 32.768kHz crystal oscillator it's made from, by way of a 15-bit (1/32768) divider. In essence, there is this one clock from which all the others come, no matter the division ratio. This is usually the HDMI / SPDIF clock if I understand correctly.
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The way to upsample is like this: To double the sample rate, add a zero between each original sample. This is called 'zero stuffing.' That gives you twice as many samples as you started with. Then run the zero-stuffed sequence through a digital LP filter. That will interpolate the data which goes between the original samples (the stuffed zero samples will be filled in with the correct interpolated values by the filter). How well the interpolation is done depends on the quality of the digital filter. Clock out the upsampled data at double the original sample rate.
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Yes, that should be another way to do it. Thus, upsampling could be achieved by way of one of the following:
1) Repeating samples (read here)
2) Inserting zeroes and filtering (padding).
3) Directly inserting estimated samples (interpolation).
4) Reconstruction and resampling.
Now, I think upsampling boxes such as the one mentioned earlier use the third method of inserting estimated samples, the algorithms for which make them expensive.
1) Repeating samples (read here)
2) Inserting zeroes and filtering (padding).
3) Directly inserting estimated samples (interpolation).
4) Reconstruction and resampling.
Now, I think upsampling boxes such as the one mentioned earlier use the third method of inserting estimated samples, the algorithms for which make them expensive.
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