I want to add a digital output to a Roland JP-8000 digital synthesizer which has only analog outputs. The form of the digital output does not matter, as long as it is possible to record the digital output directly.
In the following video it is possible to see the main board, along with the digital to analog converter at 15 minutes 20 seconds.
Roland JP-8000 Repair No / Low Audio Output - YouTube
The DAC is a NEC UPD63200, the datasheet can be accessed at UPD63200 Datasheet(PDF) - NEC
The JP-8000 service manual with some details on the circuit including the main board (starting at page 19) can be accessed below.
https://www.synthxl.com/wp-content/uploads/2018/04/Roland-JP-8000-Service-Notes.pdf
How to complete this mod and which parts do I need?
In the following video it is possible to see the main board, along with the digital to analog converter at 15 minutes 20 seconds.
Roland JP-8000 Repair No / Low Audio Output - YouTube
The DAC is a NEC UPD63200, the datasheet can be accessed at UPD63200 Datasheet(PDF) - NEC
The JP-8000 service manual with some details on the circuit including the main board (starting at page 19) can be accessed below.
https://www.synthxl.com/wp-content/uploads/2018/04/Roland-JP-8000-Service-Notes.pdf
How to complete this mod and which parts do I need?
No ready made solution I am aware of.
The data is there, its possible to get to it alright. Easy enough to see with an oscilloscope. Question is do you know how to design logic or program an FPGA do repackage your digital audio into I2S (PCM) format? I doubt you are going to find someone who wants to do it for you. That would only be the first step, too. You can't transport audio more than a very few inches in I2S format. You would have to convert it to SPDIF, TOSLINK, or AES to get it out of the box, or figure out what else you want to do with it.
The data is there, its possible to get to it alright. Easy enough to see with an oscilloscope. Question is do you know how to design logic or program an FPGA do repackage your digital audio into I2S (PCM) format? I doubt you are going to find someone who wants to do it for you. That would only be the first step, too. You can't transport audio more than a very few inches in I2S format. You would have to convert it to SPDIF, TOSLINK, or AES to get it out of the box, or figure out what else you want to do with it.
Markw4 said:
So what is needed is
- An FPGA, and a bit of coding to convert to convert the bit stream to I2S (unless there is some ready made solution).
- An audio transmitter for I2S to most likely SPIDF, although maybe the FPGA can do direct to SPIDF all the same?
- Minimal craftsmanship to put it together and of course the output + cable.
I have no slightest clue how to program the FPGA, but on the other hand good learning experience and this seems like a simple program.
I found the following parts.
FPGA:
Amazon.com: RioRand EP2C5T144 Altera Cyclone II FPGA Mini Development Board: Computers & Accessories
Transmitter:
Amazon.com: 2Pcs DIT4096 96Khz 24-Bit Digital Audio Transmitter: Industrial & Scientific
I do feel like there should be an easier solution than to need all that. Of course needing two power sources is also not ideal... Thank you again for the input!!
If you want to take on FPGAs, good for you. Digilent makes some nice development boards for Xilinx chips. If you like Altera that's fine. You might want to start looking up the documentation for the chip you are considering. Could be a quite a bit of reading.
A transmitter I like is SRC4392, although probably more than you need. You would need an MCU to program it at power up over I2C bus every time your synth is turned on.
Also, for I2S you might need to double the BCLK frequency seen at the dac chip, although it probably makes sense to measure it and the data rates at the dac chip with a scope before starting on a design to make sure you know what you are starting with. There are typically some clock resources in FPGAs you might be able to leverage for clock rate multiplication. If an unusual clock frequency for audio, SRC4392 could potentially resample it for you.
A transmitter I like is SRC4392, although probably more than you need. You would need an MCU to program it at power up over I2C bus every time your synth is turned on.
Also, for I2S you might need to double the BCLK frequency seen at the dac chip, although it probably makes sense to measure it and the data rates at the dac chip with a scope before starting on a design to make sure you know what you are starting with. There are typically some clock resources in FPGAs you might be able to leverage for clock rate multiplication. If an unusual clock frequency for audio, SRC4392 could potentially resample it for you.
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Markw4 said:
The sample rate of the synthesizer is 88.2 kHz, so I suppose BCLK is 16x that. I want to get the bit-stream from the synthesizer as is in a FIFO basis, so resampling is out of question, I hope SPIDF can accomplish this and reclock the receiving end DAC with the clock from the JP.
Would this do fine for getting the bit-stream direct to the computer for inspection / some preliminary results?
USB Logic Analyzer - 24MHz/8-Channel - TOL-15033 - SparkFun Electronics
Can this not also be a way to get the task accomplished? Get the stream through USB and write a driver to convert the stream to the appropriate format. If I get the stream at double the sample rate, I think it can still be bit perfect. Perhaps not the most professional way to get it done, but...
No, those are cheap Chinese knockoffs that don't perform at the level stated on the label. They are fast enough to capture I2C traffic, but not digital audio. You would need something more like this: Logic 8 (Black) - Saleae 8-Channel Logic Analyzer - Compatible With Windows, Mac, or Linux - Easy To Use, Ultra-Portable, Saves Time & Frustration - - Amazon.com
USB audio drivers for what OS? If for Windows, just about only Thesycon has mastered that: Thesycon - USB Audio Drivers for Windows 10, 8.1, 8 and 7
By far the most practical way would to double the bitclock with a PLL of some kind so the Left and Right channel data can be alternated in a 1-bit data stream according to LRCK (generated from MCLK). Viola: LJ or I2S PCM. It could be done in a fast enough MCU then transmitted as SPDIF. Something like sure looks like the most practical way to me.
Another way might be to use a STM32F0 MCU which may include internal resources for digital audio including USB streaming. However, their USB driver stack is reputed to be flaky, and recording is a much less common application than playback over USB. Maybe you could get it to work though and it might be a mostly one chip solution.
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I have looked at the manual and read the dac datasheet. Granted, it is a bit of a throwback to the early days of digital audio but it hardly merits the firepower of a FPGA, even if it is the smallest in the family. 4608 LE's amount to thousands of 74 series gates. It is way over the top.
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Regarding the DAC, more precisely the DAC the unit has is a NEC UPD63200GS. I was unable to find a fact sheet for that exact model, but here is an English fact sheet for UPD63200GD-A.
datasheet UPD63200GS-E1-A
So now in plain English, the DAC accepts input data in multiple different formats (see page 5). If the input of the pin 1 is 0, it seems to me that the input data actually is in the I2S format.
datasheet UPD63200GS-E1-A
So now in plain English, the DAC accepts input data in multiple different formats (see page 5). If the input of the pin 1 is 0, it seems to me that the input data actually is in the I2S format.
rfbrw said:
So by the above post, I think the audio actually is in the I2S format, all that is needed is an I2S to SPIDF or USB transmitter. I almost prefer USB as many interfaces do not have SPIDF. Adapters are acceptable, I will probably replace the headphone output with the digital connection.
The schematic shows two data lines, one for each channel. That would not be I2S.
The DAC can read data in two modes. That is indeed how it operates if the pin 1 is set to 1.
If zero is read on pin 1 instead (as I suspect it is - as it is late 90s afterall) the channel for R is used to control which channel is read and both channels are read deceptively from from the L input (or maybe I got it wrong way, but anyway). So this is I2S I think.
Charts 1-4 of the uPD63200GS sum everything up.
16 or 18 bit LSB/Right justified, pretty much the polar opposite of I2S, data clocked in serially or in parallel.
The setup for the JP-8000, chart 4, is 18 bit data clocked in in parallel.
Conversion to analogue is triggered by the falling edge of WDCK.
16 or 18 bit LSB/Right justified, pretty much the polar opposite of I2S, data clocked in serially or in parallel.
The setup for the JP-8000, chart 4, is 18 bit data clocked in in parallel.
Conversion to analogue is triggered by the falling edge of WDCK.
Interestingly, someone started a new thread on a similar subject. In that case they acquired a board from Audiophonics to try to solve the problem. However, looks like the SPDIF may be resampled. That could be okay since there looks to be an unresampled I2S output too. It all depends on how the CPLD on the board has been programmed.Moding a sega saturn to output spdif
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