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Asynchronous Sample Rate Conversion
Asynchronous Sample Rate Conversion
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Old 10th November 2005, 11:50 AM   #121
CraigBuckingham is offline CraigBuckingham
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Quote:
Originally posted by Guido Tent



on chip crosstalk

On a PCM63 it was that bad, that reclaocking wclk and data helped. On smaller packages it is different, no experience (yet)

best
Hi Guido,

For the PCM63 did you evaluate the re-clocking for each input separately and then both together?

Best regards, Craig.
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Old 18th December 2009, 06:59 AM   #122
Kurt von Kubik is offline Kurt von Kubik  Denmark
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This thread is simply amazing, and my post here shall only be for the purpose of bringing it up on the frontpage once again to remind about the brilliant work of Wherewolf.
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Old 18th December 2009, 07:10 AM   #123
Guido Tent is offline Guido Tent  Netherlands
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Quote:
Originally Posted by CraigBuckingham View Post
Hi Guido,

For the PCM63 did you evaluate the re-clocking for each input separately and then both together?

Best regards, Craig.
hello Craig,

It is about 12 years ago. We made a circuit that indeed enabled us to evaluate reclocking on data, wclk and le separately.

The Latch was most sensitive to reclocking, as expected. Data and wclk where slightly sensitive, reclcoking improved playback quality but only about 10% of the improvement made when reclocking LE.

Needless to say that one needs separate reclockers AND power supplies for all 3 signals, as we implemented in all our newest DAC designs.

best
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Old 31st January 2019, 06:22 PM   #124
pichichus is offline pichichus  Spain
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Hi there!

This post has been off for years... but I would like to raise some questions... and thank werewolf for the nice description of the topic!

First I would like to re-state the goal of the ASRC for this application... and see if I understood well all... ;

a) the goal is to use an ASRC to change the sampling rate of a digital signal transmitted to a DAC in some other distant place.
b) The idea behind this sampling rate translation is to adapt (re-sample)the data of the signal to the new clock clocking the DAC. This is, to recover the original spectrum of the signal, by re-sampling the data to the new rate at the local DAC clock (which is supposed to be close to the receiver).
c) The ASRC is called asynchronous because the ratio is incommensurate and it might fluctuate...
d) You still need two clocks, one recovered from the digital signal and the second, the local clock, for the DAC and to which you re-sample the signal

Is this right?

Now going forward...

You showed the process with a polyphase architecture... there you just use the received clock (extracted from the data stream) to compute, together with the local clock, which phase you use. Then you compute the output sample by filtering the input data with the selected phase using hardware clocked with the local clock... is this right?

A bit more forward... what about the farrow architecture?, which is more hardware efficient... was a technology limitation 15 years ago to use such scheme?

If going for a farrow... the re-sampling ratio would fluctuate, having the output clock (local) fix, right? the ASRC would correct the fluctuations of the incoming clock to the output one... right?

Do you know any implementation of such an algorithm/system?

Thanks a lot and sorry for my poor english!
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Old 6th February 2019, 08:52 AM   #125
pichichus is offline pichichus  Spain
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Hi guys, nobody interested?
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